The current work presents the first experimental demonstration of real-time Ethernet (ETH) trial services and 4K-Ultra High Definition (UHD) video application transmission over a 2λ Wavelength Division Multiplexing (WDM) analog Fiber-Wireless (FiWi) mmWave X-haul network, supporting dynamic flexible capacity allocation through an integrated silicon photonic Si ₃ N ₄ Reconfigurable Optical Add Drop Multiplexer (ROADM) and 60 GHz wireless transmission across a 7 m V-band link distance, while controlled by a Software Defined Network (SDN) controller based on Open Daylight. Analog X-haul transport of the radio signals is based on an Intermediate Frequency over Fiber (IFoF) scheme centered at 1.5 GHz using an Orthogonal Frequency Division Multiplexing (OFDM) radio-waveform with a bandwidth of 204 MHz, generated by a Field Programmable Gated Array (FPGA)-based RF System-on-Chip (SoC) processor that converts on-the-fly the real-time ETH downlink traffic to analog radio and vice-versa for the uplink. Dynamic allocation of the X-haul traffic capacity is handled through the use of the 802.1Q Virtual Local Area Network (VLAN) tag-mechanism, which controls the forwarding operation to the proper DAC and InP EML for optical modulation using Intensity Modulation/Direct Detection (IM/DD) schemes, while the wavelength routing operation is handled by the low-loss four-port Si ₃ N ₄ ROADM featuring only 2.5 dB fiber-to-fiber losses based on a cascaded MZI-interleaver design on the TriPleX platform, routing the real-time traffic to a second mmWave antenna site. Detailed measurements and traffic statistics indicate end-to-end latency of less than 260 μs and a packet loss less than 0.0054% across a dynamic range of at least 6.5 dB in the optical domain, while the high user bandwidth and signal quality are validated by an uninterrupted 4K-UHD video transmission across the FiWi X-haul mmWave transport network. The current work aims to shape a complete technology roadmap for Point-to-Multipoint FiWi transport network architectures with high spectral efficiency X-haul transport for dense areas and 5G/6G hotspots of future mmWave Centralized Radio Access Networks (C-RANs).

The Open Radio Access Network (RAN) concept has been gaining wide acceptance in recent network architectures, including 5G New Radio (NR) network deployments. Current Open RAN radio implementation efforts, aim at integrating several white-box hardware elements and executing digital processing on open-source software. When building such a software-based, 5G Open RAN platform, challenges include achieving real-time execution times for demanding computational blocks of the 5G NR physical layer processing, such as Low Density Parity Check (LDPC) decoding. In this context, having already identified both the capabilities as well as the challenges that Field-programmable Gate Arrays (FPGAs) offer for accelerating LDPC, we present our novel LDPC FPGA accelerator system. In this paper, we contribute the implementation details of our FPGA accelerator design as well as the process of integrating the accelerator with OpenAirInterface (OAI), the basis for our 5G NR platform. For the first time in the literature, we show an FPGA-based LDPC accelerator fully integrated with a complete software platform, that is able to achieve more than 1.6Gbps decoding throughput and up to 13 times faster execution times compared to single core software implementations. Finally, in our results, we show that LDPC encoding is more challenging to accelerate due to lower computational complexity.

Speeding up fast Fourier transform (FFT) computations is critical for today's real-time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures, this paper presents an address generation technique which enables a radix-b processor to access in parallel b memory banks without conflicts during each stage's computations. Using kb memory banks at each stage leads to increasing the speedup of the algorithm by a factor of kb . The address generation can be realized in each radix-b stage by the use of lookup tables of size O(kb ²) bits. The proposed technique is cost efficient and leads to the design of FFT architectures of high speedup and high sustained throughput.

Photovoltaic (PV) power production is characterized by high variability due to short-term meteorological effects such as cloud movements. These effects have a significant impact on the incident solar irradiance in PV parks. In order to control PV park performance, researchers have focused on Computer Vision and Deep Learning approaches to perform short-term irradiance forecasting using sky images. Motivated by the task of improving PV park control, the current work introduces the Image Regression Module, which produces irradiance values from sky images using image processing methods and Convolutional Neural Networks (CNNs). With the objective of enhancing the performance of CNN models on the task of irradiance estimation and forecasting, we propose an image processing method based on sun localization. Our findings show that the proposed method can consistently improve the accuracy of irradiance values produced by all the CNN models of our study, reducing the Root Mean Square Error by up to 10.44 W/m${}^2$ for the MobileNetV2 model. These findings indicate that future applications which utilize CNNs for irradiance forecasting should identify the position of the sun in the image in order to produce more accurate irradiance values. Moreover, the integration of the proposed models on an edge-oriented Field-Programmable Gate Array (FPGA) towards a smart PV park for the real-time control of PV production emphasizes their advantages.

A plethora of image and video-related applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable applications include the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) that detect objects in image frames. Aiming at contributing to the CNN accelerator solutions, the current paper focuses on the design of Field-Programmable Gate Arrays (FPGAs) for CNNs of limited feature space to improve performance, power consumption and resource utilization. The proposed design approach targets the designs that can utilize the logic and memory resources of a single FPGA device and benefit mainly the edge, mobile and on-board satellite (OBC) computing; especially their image-processing- related applications. This work exploits the proposed approach to develop an FPGA accelerator for vessel detection on a Xilinx Virtex 7 XC7VX485T FPGA device (Advanced Micro Devices, Inc, Santa Clara, CA, USA). The resulting architecture operates on RGB images of size $80\times 80$ or sliding windows; it is trained for the “Ships in Satellite Imagery” and by achieving frequency 270 MHz, completing the inference in 0.687 ms and consuming 5 watts, it validates the approach.