This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA's output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation. And the coupling coefficient (k) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power (P _sat ), and 12.9-dBm output 1-dB compression point (P1 dB). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz).

A fully integrated 76-81-GHz frequency-modulated, continuous-wave (FMCW) radar transceiver (TRX) in a 65-nm CMOS is presented. Two transmitters (TXs) and three receivers (RXs) are integrated for multiple-input multiple-output (MIMO) processing. A 38.5-GHz mixed-mode phase-locked loop (PLL) with reconfigurable loop bandwidth and a frequency doubling scheme are employed to generate the reconfigurable FMCW chirp waveforms. The coarse-to-fine-segmented current DAC is utilized to support sawtooth FMCW chirps with fast frequency ramping-down capability, and the delay lock loop (DLL)-based delay time calibration is used to improve the linearity of the embedded 2-D Vernier time-to-digital converter (TDC). Passive voltage-mode down-conversion is utilized to improve the RX linearity against TX leakage and short-range interference. A bottom-switching Gilbert-type modulator in the TX is proposed to realize the bi-phase modulation, and the magnetically coupled resonator technique is used to effectively expand the link bandwidth. The measurement results show that the FMCW TRX could generate reconfigurable chirps with the bandwidth from 250 MHz to 4 GHz and the period from 30 μs to 10 ms. The root-mean-square (rms) frequency error is 110 kHz for a sawtooth chirp with 4-GHz bandwidth and 300-μs period. The TX maximum output power is 13.4 dBm and is adjustable within 3 dB by reconfiguring its low dropout regulator (LDO) voltage. The RX achieves a 15.3-dB noise figure at 600-kHz IF and a -8.5-dBm RF input-referred P1dB. The overall power consumption is 921 mW, with two TXs and three RXs powered ON. Based on the proposed TRX chip, prototype hardware and a data process algorithm are developed. Real-time experimental results show that the distance and the angular resolution of the MIMO radar achieved are 5 cm and 9$°, respectively.

A $D$ -band joint radar-communication complementary metal–oxide–semiconductor (CMOS) transceiver featuring a dual-function mode multiplexer, a power-combining PA with high output power, a current choking high-gain mixer, a two-point modulation (TPM) frequency-modulated continuous-wave (FMCW) digital phase-locked loop (PLL) with a dual-core DCO, and a wideband I/Q local oscillator (LO) generator is implemented in 28-nm CMOS technology. In the radar mode, the RF front end demonstrates 46-GHz bandwidth (BW), and the on-chip PLL/LO generated FMCW chirp achieves a BW of 30 GHz and a slope of 30 GHz/50 $\mu$ s. In the communication mode, the transceiver including the analog baseband realizes 20-GHz BW, and the image rejection ratio (IRR) is better than 40 dB. The measured transmitter (TX) saturated output power is 13 dBm, and the output 1-dB compression point (OP1dB) is 8.3 dBm. The measured typical PLL phase noise is $-$ 111.3 dBc/Hz at a 1-MHz offset from an 11.69-GHz carrier frequency. The TX-to-RX over-the-air (OTA) modulation–demodulation measurement with QPSK and 16-QAM signals shows the error vector magnitude (EVM) of $-$ 16.5 and $-$ 19.7 dB, respectively.

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-mum CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 mum CMOS.

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signal bandwidth, and a fractional-N frequency synthesizer. Passive current mixer is employed in the receiver to improve the linearity and avoid the sensitivity degradation due to 1/f noise. Automatic I/Q imbalance calibration is integrated to improve image rejection ratio (IRR) with the aid of external FPGA. The transmitter is implemented in the digital polar architecture to improve the narrow-band spectrum purity, integrated with an inverse Class-D digital power amplifier (DPA) to achieve high output power and efficiency. A Class-C voltage-controlled oscillator with automatic frequency control assisted the dynamic gate biasing technique is used in the fractional-N PLL frequency synthesizer. Two prototypes are implemented in 180-nm CMOS. By optimizing analog baseband configuration in the receiver and utilizing the revised thermometer-coding and binary-coding-based array placement in the DPA, the receiver achieves 4.0-dB noise figure, 48-dB IRR, and 60-dB PGA dynamic range, and the DPA outputs 23.2dBm maximum saturation power with 44.5% PAE. Furthermore, the transmitter system verifications demonstrate 3.87% error-vector magnitude (EVM) for 891 MHz π/4-DQPSK signals at 18.87-dBm output power with -40-dBc out-of-band rejection. The transmitter achieves a dynamic range from -35 to 20 dBm when the demodulation EVM threshold of the system is set to 10%.

In this article, we propose a voltage-controlled oscillator (VCO) with a single three-coil transformer, featuring a common-mode (CM) resonance expansion and intrinsic differential 2nd harmonic output. In addition to a conventional transformer-based class-F resonator, an internal third coil is added to manipulate the CM response. On one hand, it expands the CM resonance bandwidth, eliminating the need for manual harmonic tuning to align the 2nd harmonic resonance. On the other hand, it creates a simultaneous wideband differential response at the 2nd harmonic frequency, therefore, the power consumption of the extra frequency doubler can be saved. Using the proposed stacked 8-shape inductor topology, the third coil can be placed inside the class-F transformer without consuming an extra chip area. Fabricated in a 65-nm CMOS process, the measured tuning range of the proposed VCO is 21.1%, from 12.3 to 15.2 GHz. The proposed VCO achieves a peak phase noise (PN) performance of $-$ 118.0 and $-$ 111.9 dBc/Hz at 1 MHz offset for fundamental frequency and 2nd harmonic, respectively, the corresponding peak figure-of-merit (FoM) of which is 190.4 and 190.1 dBc/Hz, respectively. The VCO consumes a power of 8.4–9.6 mW, while occupying a small area of 0.06 mm $^{2}$ thanks to the stacked 8-shape inductor topology.