Kyriakos Zoiros

Dr. Kyriakos Zoiros

Department of Electrical and Computer Engineering, Lightwave Communications Research Group, Democritus University of Thrace, Xanthi GR 67 100, Greece

Research Focus & Metrics

Academic Career Length

24Years (2003-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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15 September 2020 in IEEE Journal of Selected Topics in Quantum Electronics
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DFDimitrios E. Fouskidis
Dimitrios E. Fouskidis
Kyriakos ZoirosKyriakos Zoiros
Kyriakos Zoiros
AHAntonios Hatziefremidis
Antonios Hatziefremidis
All-optical logic gates are indispensable modules for executing exclusively by means of light fundamental Boolean operations. Despite intense research in this field, most efforts have not treated these gates in a joint design and operating manner. This causes waste of hardware resources and lack of versatility. In this paper, we theoretically investigate, assess and demonstrate the feasibility of implementing all-optically multiple logic gates (AND, NOR, OR, NOT) at 160 Gb/s by means of a single quantum-dot semiconductor optical amplifier (QD-SOA) and a concatenated optical filter. We follow a methodical approach and conduct a thorough numerical study to derive rules for the selection of the critical operating parameters so that appropriate performance criteria defined for each gate are made acceptable. The intersection of the permissible bounds allows us to specify a combination of parameters' values which is the same for all gates and guarantees the execution of the corresponding Boolean functions with logically correct and high quality outcome. The proposed scheme can be reconfigured to realize the different gates at 160 Gb/s without changes in its basic setup or driving conditions. This is achieved simply by detuning the optical filter according to the design guidelines of each gate.


15 September 2020 in Journal of Computational Electronics
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JRJayanta K. Rakshit
Jayanta K. Rakshit
Kyriakos ZoirosKyriakos Zoiros
Kyriakos Zoiros
GBGaurav K. Bharti
Gaurav K. Bharti

1 July 2004 in Optical Engineering
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THThanassis Houbavlis
Thanassis Houbavlis
Kyriakos ZoirosKyriakos Zoiros
Kyriakos Zoiros
The switching characteristics of a semiconductor optical amplifier (SOA)-assisted Sagnac gate are analyzed in terms of their critical performance parameters for full duty cycle operation from 10 to 40 GHz. Within this frame, the influence of the control pulse width, as well as of the SOA gain recovery time on the switching energy and the contrast ratio, is examined through numerical simulation. The obtained results show that full switching operation at 40 GHz or higher is feasible either by deploying gain recovery reduction techniques in bulk SOAs, or other alternative technologically advanced optical devices, such as quantum-dot SOAs. © 2004 Society of Photo-Optical Instrumentation Engineers.

1 December 2003 in Optical Engineering
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Kyriakos ZoirosKyriakos Zoiros
Kyriakos Zoiros
THT. Houbavlis
T. Houbavlis
All-optical Boolean XOR operation is demonstrated on pseudo-data patterns at 20 Gb/s with a three optical input semiconductor optical amplifier-assisted Sagnac switch. Bit pattern switching has been achieved with low energies of the incoming clock and data pulses and low pattern dependence on the switched-out pulses. © 2003 Society of Photo-Optical Instrumentation Engineers.

1 August 2007 in Optical Engineering
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JVJohn Vardakas
John Vardakas
Kyriakos ZoirosKyriakos Zoiros
Kyriakos Zoiros
A theoretical model is developed and exploited for characterizing the behavior of an all-optical circuit that deploys a Fabry-Pérot filter (FPF) and a semiconductor optical amplifier (SOA)-assisted Sagnac switch driven by an intense continuous wave (cw) holding beam to extract the clock signal from a received ultra-fast data stream. The role of each unit is thoroughly studied, and its understanding allows us to identify the critical operational parameters, which include the cw power, the energy of the data pulses, the SOA small signal gain, carrier lifetime and linewidth enhancement factor, the Sagnac loop asymmetry, and the finesse of the FPF. By means of numerical simulation, an extensive set of diagrams is derived, and from their interpretation the impact of these key factors on the amplitude modulation of the extracted clock pulses is investigated and evaluated. This process enables us to appropriately select and combine them to ensure enhanced performance concerning the defined quality metric, first at 10Gb∕s and then at 40Gb∕s. The final outcome demonstrates the technological feasibility and effectiveness of the proposed clock recovery scheme. The obtained results may be useful for theoretically addressing various all-optical signal processing tasks, whose proper execution relies decisively on clock recovery.