The relationship between the magnitude of the piezoelectric field and the degree of lattice constant mismatch is investigated via low‐temperature photoluminescence measurements of the quantum‐confined Stark effect for a series of (111)B Al_0.15Ga_0.85As‐In_yGa_1−yAs pseudomorphic quantum well heterostructures. The experimental strain‐induced electric field values agree well with theoretical calculations for indium mole fractions in the range 0.037≤y≤0.09. In addition, an anomalous saturation of the photoluminescence transition energy is observed at values of applied voltage greater than that required to nullify the piezoelectric field, despite the indication from separate electroreflectance measurements that the net electric field within the quantum well reverses polarity under similar electrical biasing conditions.

The programming of partial polarization in ferroelectric (FE) hafnium zirconate (HZO) capacitors is shown to depend on the delay between FE reset and the polarization write pulse (delay-before-write), revealing a subtle history dependence. Programming is substantially independent of delays inserted after the write and before the read (delay-before-read), with no decay in partial polarization observed from 1 μs up to 260 ms. We further show that nonsaturation in FE polarization can be introduced if the pulse protocol is not strictly symmetric, where strictly symmetric means that the integral of the voltage waveform over a single measurement cycle is zero. The delay-before-write dependence in HZO is compared with lead-zirconium-titanate (PZT) capacitors used in FE random access memory (FRAM) which shows much weaker dependence. The delay dependence is attributed to the dynamics of subcritical nuclei formation in nucleation limited switching. For the first time, the decay of subcritical nuclei in HZO is shown to be observable up to 1 s, and an upper bound on their volume is estimated to be ~10 nm³, corresponding to ~4x4 x4 unit cells.

An overview of the steps employed to advance non-volatile Pb(Zr_xTi_1−x)O₃-based materials from parallel capacitor array test structures to embedded 130 nm (1.5 V operation) memory product release is presented. Specific development stages include parallel capacitor array evaluation, capacitor characterization array development, memory macro creation and measurement, and initial product design and qualification. Representative data, learning goals, and critical outputs will be presented for each development phase. We note that the cost and complexity of the development effort increase dramatically as the new technology approaches high-volume manufacturing. We hope that the documentation of our experiences in this manuscript may be of assistance to those teams striving to create the next generations of non-volatile embedded memory technology.

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 /spl mu/m/sup 2/) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125/spl deg/C bake was observed.