Convolutional neural networks (CNN) and long short-term memory (LSTM) have gained wide recognition in the field of natural language processing. However, due to the pre- and post-dependence of natural language structure, relying solely on CNN to implement text categorization will ignore the contextual meaning of words and bidirectional long short-term memory (BiLSTM). The feature fusion model is divided into a multiple attention (MATT) CNN model and a bi-directional gated recurrent unit (BiGRU) model. The CNN model inputs the word vector (word vector attention, part of speech attention, position attention) that has been labeled by the attention mechanism into our multi-attention mechanism CNN model. Obtaining the influence intensity of the target keyword on the sentiment polarity of the sentence, and forming the first dimension of the sentiment classification, the BiGRU model replaces the original BiLSTM and extracts the global semantic features of the sentence level to form the second dimension of sentiment classification. Then, using PCA to reduce the dimension of the two-dimensional fusion vector, we finally obtain a classification result combining two dimensions of keywords and sentences. The experimental results show that the proposed MATT-CNN+BiGRU fusion model has 5.94% and 11.01% higher classification accuracy on the MRD and SemEval2016 datasets, respectively, than the mainstream CNN+BiLSTM method.

Convolutional Neural Networks (CNNs) have become one of the most successful machine learning techniques for image and video processing. The most computationally intensive part of the CNN is the convolutional layers, which have the multi-channel image and multiple kernels. However, due to the network pruning operation and the application of RELU activation function operation in the training process, numerous zero values are generated in the network. This paper proposes the convolution split compression calculation (CSCC) algorithm, which improves the performance of the convolution layer by utilizing the sparse characteristic of the feature map. In the CSCC algorithm, first, the feature map is directly converted into a sparse matrix of compressed sparse row (CSR) format, which avoids expanding feature map to an intermediate matrix and reduces the memory space consumption. Second, the convolution kernel is converted into a vector. Finally, the convolution result is obtained by the sparse matrix vector multiplication (SpMV). The experimental results show that the CSCC algorithm has a good advantage in computation speed and memory consumption compared with the other convolution algorithms.

Motion estimation (ME) is a kernel algorithm in many video applications. Full search integer ME (FSIME) can find the best result but it usually takes plenty of time. Traditionally, only intra-frame data reuse is considered for FSIME. In this paper, a new inter-frame data reuse method is proposed to further utilize inter-frame data reuse for true ME. ME in frame rate up-conversion (FRUC-ME), a kind of true ME, is used as a case study. For FRUC-ME with the new inter-frame data reuse method, a frame is loaded to the on-chip buffer only once instead of twice and used for two interpolated frames. Two levels of the new method are proposed, Inter-D and new Inter-E, which give a good tradeoff between off-chip memory bandwidth and on-chip buffer size. New data access order is used to implement the new data reuse method. The proposed data reuse method (Inter-D) demands less off-chip memory bandwidth than its intra-frame counterpart (Intra-D), and the off-chip memory traffic and power consumption are both reduced by 37.5% for FRUC-ME.

2-D-to-3-D conversion is one way to make full use of 2-D contents to produce 3-D contents. Real-time 2-D-to-3-D conversion is required for 3-D consumer electronic devices, which demands fast processing speed especially for high-definition videos. In this paper, we propose a reconfigurable VLSI architecture for real-time 2-D-to-3-D conversion. Two different depth-retrieval methods are implemented in this architecture in order to support the choice of a best method or combination of different methods. The proposed architecture can also support different resolutions (4K, 1080p, and 720p) and the original view can be configured as either left view or right view. In order to overcome the problem of “Memory Wall”, we propose a data reuse method to reduce memory traffic for the proposed architecture so that the overall performance is improved to realize real-time conversion. The experiment result shows that the implemented 2-D-to-3-D architecture can achieve state-of-the-art throughput (4K@30f/s).

Stacked DRAM used as the last-level caches (LLCs) in multicore systems delivers performance enhancement due to its capacity benefit. While the performance of LLC depends heavily upon its block replacement policy, the conventional replacement policy needs redesigning to exploit the best of DRAM cache and avoid its drawbacks. The existing DRAM cache insertion policy blindly forwards victim lines replaced from L3 to the off-chip memory, regardless of the potential for increased hits by placing a fraction of them in the DRAM cache. Nevertheless, a naïve design that steers all dirty victims to the DRAM cache introduces excessive writeback traffic, which aggravates capacity misses and DRAM interference. To leverage insertions in terms of writeback or fill requests, we propose a collective writeback and fill policy that adapts to the distinct access patterns of heterogeneous workloads based on runtime misses and writeback efficiency. The synthesis result shows that the new policy has only a small hardware overhead. According to the experimental results on the gem5 simulator, the new policy increases harmonic instruction per cycle throughput by 18%, 11.6%, and 11.7%, respectively, compared with the Always Writeback (AW)-Always Fill policy, Never Writeback Adaptive DRAM Placement policy, and AW Adaptive DRAM Placement policy on 64-MB alloy cache, while the improvement is 19.3%, 13.7%, and 14.5% on 64-MB MissMap cache.