In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent on-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.

An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.

A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.

A novel approach to optimize tunnel field-effect transistors (TFETs) by technology computer-aided design simulations is reported. The most interesting outcome of our design effort is a dual-metal-gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain-current decade or more. The DMG-TFET simultaneously fulfills both the low-standby-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.

We investigate the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver. In both cases, we first solve the coupled Schrodinger-Poisson equations to extract the profiles of the 1-D subbands along the channel; next, the coupled multisubband Boltzmann equations are tackled with the two different procedures. A very good agreement is achieved between the two approaches to the transport problem in terms of mobility, drain-current, and internal physical quantities, such as carrier-distribution functions and average velocities. Some peculiar features of the low-field mobility as a function of the wire diameter and gate bias are discussed and justified based on the subband energy and wave-function behavior within the cylindrical geometry of the nanowire, as well as the heavy degeneracy of the electron gas at large gate biases.

A number of experiments have recently appeared in the literature that extensively investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body silicon-on-insulator (SOI) MOSFETs. The aim of this paper is to develop a compact model, suited for implementation in device- simulation tools, which accurately predicts the low-field mobility in SOI single- and double-gate MOSFETs with Si thicknesses down to 2.48 nm. Such a model is still missing in the literature, despite its importance to predict the performance of present and future devices based on ultrathin silicon layers.