Impedance Cardiography (ICG) is a non-invasive method for monitoring cardiac dynamics using Electrical Bioimpedance (EBI) measurements. Since its appearance more than 40 years ago, ICG has been used for assessing hemodynamic parameters. This paper present a measurement system based on two System on Chip (SoC) solutions and Raspberry PI, implementing both a full 3-lead ECG recorder and an impedance cardiographer, for educational and research development purposes. Raspberry PI is a platform supporting Do-It-Yourself project and education applications across the world. The development is part of Biosignal PI, an open hardware platform focusing in quick prototyping of physiological measurement instrumentation. The SoC used for sensing cardiac biopotential is the ADAS1000, and for the EBI measurement is the AD5933. The recording were wirelessly transmitted through Bluetooth to a PC, where the waveforms were displayed, and hemodynamic parameters such as heart rate, stroke volume, ejection time and cardiac output were extracted from the ICG and ECG recordings. These results show how Raspberry PI can be used for quick prototyping using relatively widely available and affordable components, for supporting developers in research and engineering education. The design and development documents, will be available on www.BiosignalPI.com, for open access under a Non Commercial-Share A like 4.0 International License.

In this paper, a transducer based instrument for fingertip touch force is developed. As a diagnostic tool, the system was coupled with an EMG analog signal processor, which is considered as the main basis of evaluation for motor function impairment. A software program is developed to analyze EMG signal during fingertips effort to obtain valid characteristic parameters with spectral analysis. These parameters are associated with a low cost grip transducer based on Hall Effect component developed for the improvement of fingertip movement during holding objects or training exercises. Thus, the changes on each sensor signal can be detected and monitored with the software interface. The output signal and the EMG analog processor are feeding a high resolution data acquisition system of National Instrument. Preliminary experimental tests have been carried out for the fingertip force grasping according to the adductor Pollicis muscle (AdP) for controlling the adductive motion of the thumb. The experimental results show that the changes of dynamic fingertip force affect the muscle.

This paper presents an integrated optical receiver which consists of an integrated photodetector, and a transimpedance circuit. A series inductive peaking is used for enhancing the bandwidth. The proposed structure operates at a data rate of 10 Gb/s with a BER of Iff²⁰ and was implemented in a 0.35 μm CMOS process. The integrated photodiode has a capacitance of 0.01 pF which permits to the structure to achieve a wide bandwidth (5.75 GHz) with only one inductor before the last stage; hence a smaller silicon area is maintained. The proposed TIA has a gain of36.56 dBΩ (67.57 KΩ), and an input courant noise level of about 25.8 pA/Hz^0.5. It consumes a DC power of 87.4 mW from 3.3 V supply voltage.

The motion control of a planar manipulator with two flexible arms is studied. Dynamics are developed in Lagrange's formulation. A novel control system structure is proposed to control the joint position and velocity as well as deflection of the tip for each arm. First, nonlinear control law based on the equations of motion of the robot is presented and stability analysis is studied. Then, an adaptive neural controller is implemented to compensate structured and unstructured uncertainties. Efficiency of the new controller obtained by combining the two control laws is tested facing an important variation of the dynamic parameters of the flexible manipulator and compared to the nonlinear control taken solely. Simulation results show the effectiveness of the control strategy proposed.

A new architecture for a 8-bit flash nonlinear analog to digital converter (NADC) with reduced complexity is proposed. The design of this NADC is module oriented using an optimal artificial neural network (NN) modelization. The 8-bit NADC is developed by using 4-bit NADC with appropriates analog circuits. The 8-bit NADC neural architecture was optimized in view to field programmable gate array (FPGA) implementation using very high-speed integrated circuit hardware description language (VHDL). Tests results are given to verify the implemented proposed NADC.