Neural signal recording demands compact, low-power, high-performance amplifiers, to enable large-scale, multi-channel electrode arrays. This work presents a bioamplifier optimized for action potential detection, designed using TSMC 28 nm HPC CMOS technology. The amplifier integrates an active low-pass filter, eliminating bulky DC-blocking capacitors and significantly reducing the size and power consumption. It achieved a high input impedance of 105.5 GΩ, ensuring minimal signal attenuation. Simulation and measurement results demonstrated a mid-band gain of 58 dB, a −3 dB bandwidth of 7 kHz, and an input-referred noise of 11.1 μ${\mathrm{V}}_{\mathrm{rms}}$, corresponding to a noise efficiency factor (NEF) of 8.4. The design occupies a compact area of 2500 μ$m^2$, making it smaller than previous implementations for similar applications. Additionally, it operates with an ultra-low power consumption of 3.4 μW from a 1.2 V supply, yielding a power efficiency factor (PEF) of 85 and an area efficiency factor of 0.21. These features make the proposed amplifier well suited for multi-site in-skull neural recording systems, addressing critical constraints regarding miniaturization and power efficiency.

This paper presents an innovative ultra-low power photoplethysmography (PPG) readout circuit designed for driving red (R) and infrared (IR) LEDs and extracting a PPG signal with high energy efficiency. Implemented in TSMC 130 nm CMOS technology, this new PPG sensor improves upon previous solutions in several ways including: by (1) employing a current buffer between the photodiode (PD) and the transimpedance amplifier (TIA) to isolate the PD’s substantial parasitic capacitance, which among others, allows using shorter duty cycles than other solutions, thereby reducing the power consumption significantly, (2) utilizing a class AB output stage in the TIA to enhance the dynamic range and cope with large DC input components, and (3) using a novel LED driver circuit, which relaxes the power supply requirements and, consequently, reduces the overall power consumption. Employing the mentioned techniques, the TIA achieves a wide input current range of 180 μA, preventing circuit saturation. Also, with a 1% duty cycle (100 μs) and a PWM frequency of 100 Hz, the measured power consumption is 0.3 mW, with typical driving currents of 9 mA for infrared, and 15 mA for red LEDs. The fabricated chip was incorporated into a finger-clip PPG sensor integrating LEDs and a photodiode for facilitating test and validation in realistic conditions with 5 participants.

Resistive MEMS sensors have become increasingly significant in biomedical and bioenvironmental monitoring due to their compact dimensions, low energy demand, and high sensitivity. Despite structural simplicity and integration benefits, these sensors face performance constraints arising from intrinsic nonidealities such as nonlinearity, thermal drift, parasitic interactions, and process mismatches. These limitations intensify at micro and nanoscale dimensions and generate substantial DC offset in the output. This review presents a systematic analysis of resistive sensor architectures, including single resistor, half bridge, and full bridge configurations, and evaluates their susceptibility to distortion and noise through analytical modeling. Comparative assessment reveals tradeoffs in sensitivity, linearity, noise resilience, and thermal stability. The paper also examines advanced readout methodologies designed for precision measurement, low power operation, and compact integration, including voltage to voltage, voltage to frequency, resistance to digital, and RC delay based interfaces. Particular emphasis is placed on DC offset compensation strategies that address sensor nonidealities, such as resistive, current driven, and capacitive DAC techniques, implemented across different stages of the signal chain. These approaches are critically appraised for their effectiveness in extending dynamic range, reducing energy consumption, and preserving signal fidelity in implantable and wearable platforms. The survey synthesizes recent designs and proposes a classification framework to guide the selection of interface and compensation strategies designed to sensor topology and application constraints. By integrating theoretical insights with practical design considerations, this work provides a comprehensive reference for developing robust, precise, and energy efficient resistive sensor interfaces.

This paper presents an ultra-compact, energy-efficient IR-UWB transmitter designed in 28 nm CMOS technology for high-density, wireless neural recording implants. The proposed architecture employs a tunable ring VCO-based pulse generator with a differential antenna driver, enabling wide frequency adaptability across lower and upper UWB bands while maintaining compliance with FCC, ECC, and Japanese spectrum masks. A startup-optimized pulse generation scheme and a high-efficiency output stage-both proposed for the first time in this work-enhance transient response and boost output amplitude. The transmitter achieves a peak-to-peak output voltage as high as 1.33 V with a 1.2 V supply, and delivers output power and energy efficiency up to −7.5 dBm and 3.7%, respectively. It supports IEEE 802.15.6 channels 1-9 with tunable bandwidth and occupies only 0.0019 mm 2 of silicon area. These features make it particularly suitable for deep cortical implants where high output amplitude and power efficiency are essential under stringent power and size constraints.

This paper presents a fully-CMOS, tunable impulse radio ultra-wideband (IR-UWB) transmitter for high-density implantable neural recording systems. Fabricated in 28 nm CMOS technology, the transmitter features an ultra-compact edge-combining architecture based on a digitally tunable impulse response filter (IRF) occupying only 0.0027 mm 2. The measured output exhibits a central frequency of 4.5 GHz with a 10-dB bandwidth of 3.6 GHz, providing robust spectral performance. It achieves 1 GHz frequency tunability by adjusting pulse widths from 650 ps to 800 ps, ensuring compliance with FCC spectral masks. A current-starved ring VCO (CSRVCO), with a compact 150 µm 2 layout, serves as the clock source, offering wide frequency tuning, low power consumption, and enhanced output power. The transmitter employs On-Off Keying (OOK) modulation and delivers a peak output amplitude of 660 mV with up to 5.1% energy efficiency. At a 20 MHz pulse repetition rate, the transmitter consumes only 78 µW while producing −24.5 dBm of output power. Measurement results confirm compliance with FCC regulations and suitability for deeply implanted biomedical applications. The design achieves a competitive figure of merit (FoM) of 0.017 (mm 2 • pJ)/(b • V), demonstrating its scalability and efficiency compared to prior state-of-the-art solutions.

This letter presents a compact and energy-efficient impulse radio ultra-wideband (IR-UWB) transmitter implemented in 28 nm CMOS technology, tailored for on-cortex neural implants. The transmitter features a carrier-based pulse generation scheme with a novel cross-coupled output stage that boosts the output swing without requiring off-chip components. It delivers a peak-to-peak amplitude of 1.79 V with a tunable center frequency from 5.2 to 6.1 GHz and achieves a peak output power of -10.5 dBm under a 1.5 ns pulse width. The energy consumption is 23.8 pJ/bit at 40 Mbps, yielding a competitive FoME of 0.2. This solution meets spectral regulations and power constraints, making it suitable for scalable wireless neural recording systems.