Exploring a nanotheranostic agent with image guided highly efficient therapeutic properties is greatly significant for tumor screening and treatment. Herein, we construct a novel nanoplatform, composed of low cost bovine serum albumin (BSA), sulfonamides (SAs) and iron porphyrin nanoscale metal organic frameworks (NMOFs), which possesses the capability of active targeting to tumor cells and magnetic resonance imaging (MRI) can be used to guide synergetic photodynamic/photothermal therapy. These constructed BSA/SAs–NMOF nanoplatforms can be accumulated more at tumor sites due to modification of the nanoparticles with BSA/SA complexes, allowing this system to achieve long circulation in vivo and to actively target to carbonic anhydrase (CA) IX of tumor cells by the SAs. Moreover, the magnetic iron ion and porphyrin serve as the metal centre and organic ligand of novel NMOFs which exhibit a T₁–T₂ weighted MRI effect (r₁ = 2.7 mM⁻¹ s⁻¹ and r₂ = 19.68 mM⁻¹ s⁻¹) and allow synergetic photodynamic/photothermal therapy of tumors. In vitro reactive oxygen species (ROS) detection and photothermal temperature change results revealed that these BSA/SAs–NMOF nanoplatforms could exhibit a great PDT effect in tumor cells, even under hypoxic conditions, and a remarkable PTT effect with a photothermal conversion efficiency of 40.53%. What's more, there was a greater fatality rate of 4T1 cancer cells in the single wavelength induced PDT & PTT group (95%) than in the PDT or PTT monotherapy groups (nearly 80%), and the growth of a solid tumor was more effectively inhibited by PDT & PTT than by single PTT or PDT. This work provides a novel nanoplatform for targeting tumor hypoxia and achieved highly efficient treatment of tumors based on PDT and PTT.

Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values.

LoRa is a promising choice for deploying an IoT network due to its lightweight feature and the extensive support by LoRa Alliance. However, as a fundamental part of LoRa, the typical LoRaWAN protocol confronts severe security challenges because it insecurely utilizes AES-128 to support the low-cost feature. In this article, we propose a systematic solution that is compatible with LoRaWAN for IoT applications. We extend the standard LoRaWAN protocol with public-key infrastructures. Public-key features like key exchange and authentication are supported by lightweight hardware implementations of SHA-2, ECDH, EdDSA, and TRNG. A lightweight RISC-V processor with a security coprocessor is implemented and verified using FPGA technology. The security protocol and the prototype hardware system are validated and evaluated on practical applications from our industrial partner. The prototyped development board consumes a static power of 0.116 W and a dynamic power of 0.206 W. The proposed system can achieve a $5.6\times $ – $144.7\times $ speed up and reduce memory usage by $2.4\times $ – $12.3\times $ for security computations.

Keccak is widely used in lattice-based cryptography (LBC) and its impact to the overall running time in LBC scheme can be predominant on platforms lacking dedicated SHA-3 instructions. This holds true on embedded devices for Kyber and Dilithium, two LBC schemes selected by NIST to be standardized as quantumsafe cryptographic algorithms. While extensive work has been done to optimize the polynomial arithmetic in these schemes, it was generally assumed that Keccak implementations were already optimal and left little room for enhancement.In this paper, we revisit various optimization techniques for both Keccak and Dilithium on two ARMv7-M processors, i.e., Cortex-M3 and M4. For Keccak, we improve its efficiency using two architecture-specific optimizations, namely lazy rotation and memory access pipelining, on ARMv7-M processors. These optimizations yield performance gains of up to 24.78% and 21.4% for the largest Keccak permutation instance on Cortex-M3 and M4, respectively. As for Dilithium, we first apply the multi-moduli NTT for the small polynomial multiplication cti on Cortex-M3. Then, we thoroughly integrate the efficient Plantard arithmetic to the 16-bit NTTs for computing the small polynomial multiplications csi and cti on Cortex-M3 and M4. We show that the multi-moduli NTT combined with the efficient Plantard arithmetic could obtain significant speed-ups for the small polynomial multiplications of Dilithium on Cortex-M3. Combining all the aforementioned optimizations for both Keccak and Dilithium, we obtain 15.44% ∼ 23.75% and 13.94% ∼ 15.52% speed-ups for Dilithium on Cortex-M3 and M4, respectively. Furthermore, we also demonstrate that the Keccak optimizations yield 13.35% to 15.00% speed-ups for Kyber, and our Keccak optimizations decrease the proportion of time spent on hashing in Dilithium and Kyber by 2.46% ∼ 5.03% on Cortex-M4.

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of 1.75x. In image training tasks, the proposed hardware architecture helps to achieve up to 1.67x speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by 1.30x and 1.04x respectively.