Horizontally stacked Ge-nanosheet gate-all-around FETs (GAAFETs) are demonstrated for the first time. The Ge/Si multilayers instead of the typically used Ge/SiGe ones were epitaxially grown as the starting material. To avoid island growth, the Ge/Si multilayers were epitaxially grown at a low temperature. Using megasonic agitation, the Si in Ge/Si multilayers can be easily etched with good selectivity using a tetramethyl–Vammonium–Vhydroxide (TMAH) water solution at an appropriate temperature. Finally, the p- and n-GAAFETs of gate length (LG) 90 nm were fabricated, and drive currents Ion of 1650 μA/μm and 1510 μA/μm (per width of channel footprint) were achieved, respectively.

A record high electron mobility of 698 cm2/V∙s in a tensile-strained Ge0.96Sn0.04 nMOSFET is demonstrated in this letter. High-quality GeSn films were epitaxially grown by low-temperature chemical vapor deposition. Different strain conditions in the active GeSn layers were achieved by Ge or GeSn relaxed buffers. A mesa FET structure was used to effectively reduce the OFF leakage by a recessed p/n junction in Ge. The ION/IOFF ratio in the mesa GeSn FETs is boosted by a factor of 100 compared to conventional planar devices. As the GeSn film becomes more tensile strained, the channel mobility is enhanced, which could be attributed to a higher carrier population in the Γ valley.

This research presents the optimization and proposal of P- and N-type 3-stacked Si_0.8Ge_0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si_0.8Ge_0.2 FinFET, and Si_0.8Ge_0.2/Si SL FinFET, were comprehensively compared with HfO₂ = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si_0.8Ge_0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SS_avg) of 88 mV/dec, the highest maximum transconductance (G_{m, max}) of 375.2 μS/μm, and the highest ON–OFF current ratio (I_ON/I_OFF), approximately 10⁶ at V_OV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal–oxide–semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si_0.8Ge_0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si_0.8Ge_0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.

The fabrication of vertically stacked SiGe nanosheet (NS) field-effect transistors (FETs) was demonstrated in this study. The key process technologies involved in this device fabrication are low pressure chemical vapor deposition SiGe/Si multilayer epitaxy, selective etching of Si layers over SiGe layers using tetramethyl-ammonium-hydroxide wet solution, and atomic layer deposition of Y₂O₃ gate dielectric. For the fabricated stacked SiGe NS p-GAAFETs with a gate length of 90 nm, I_ON/I_OFF ratio of around 5.0 × 10⁵ and subthreshold swing of 75 mV/dec were confirmed via electrical measurements. Moreover, owing to its high quality of Y₂O₃ gate dielectric, the device showed a very small drain-induced barrier-lowering phenomenon. These designs can improve the gate controllability of channel and device characteristics.

We successfully fabricate the Si0.8Ge0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio ( 10×) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the conventional Si FinFET, our proposed SiGe ultra-thin FinFETs (Si0.8Ge0.2 UT-FinFET) at VD = 0.75 V & VG = 1.5 V shows higher ON-state current (1 mA/fin), even achieve lower OFF-state current (0.2 nA/fin) and steep subthreshold slope (SS) of 76 mV/decade, which is owing to the better gate control given by the ultra-thin fin channel. In addition, this work also exhibits the suppression of short channel effect (SCE) with very small drain induced barrier-lowering (DIBL) of 4 mV/V.