The rapid growth of the Internet of Things (IoT) and smart devices has led to an increasing demand for real-time data processing at the edge of networks closer to the source of data generation. This review paper introduces how artificial intelligence (AI) can be integrated with edge computing to enable efficient and scalable object recognition applications. It covers the key considerations of employing deep learning on edge computing devices, such as selecting edge devices, deep learning frameworks, lightweight deep learning models, hardware optimization, and performance metrics. An example of an application is also presented in this article, which is about real-time power transmission line detection using edge computing devices. The evaluation results show the significance of implementing lightweight models and model compression techniques such as quantized Tiny YOLOv7. It also shows the hardware performance on some edge devices, such as Raspberry Pi and Jetson platforms. Through practical examples, readers will gain insights into designing and implementing AI-powered edge solutions for various object recognition use cases, including smart surveillance, autonomous vehicles, and industrial automation. The review concludes by addressing emerging trends, such as federated learning and hardware accelerators, which are set to shape the future of AI on edge computing for object recognition.

This paper presents a comprehensive hardware accelerator architecture of YOLOv3-Tiny targeted for low-cost FPGA with a high frame rate, high accuracy, and low latency. The proposed accelerator implements all YOLO layers in hardware including zero pad layer, convolution layer, leaky ReLU layer, batch normalization layer, max-pooling layer, and up-sampling layer. The architecture is built based on data flow and control flow hybrid architecture. The data preparation and computation process work asynchronously using the data flow paradigm, while the overall governing process is controlled by proposed custom instruction set which adopts the principle of control flow paradigm. The principle of General Matrix Multiplication (GEMM) is adopted to compute the convolution process. We designed a GEMM processor using an optimum size of systolic array architecture. The systolic core is small and the overall architecture supports the multicore system, making it scalable to be implemented on larger size FPGAs. We also proposed a hardware architecture for mapping feature maps into matrix form for GEMM convolution which can save on-chip memory space. Lastly, we modified the original YOLO algorithm to further optimize it in our hardware. The modification includes reducing the bit precision to reduce memory space and bandwidth requirement, merging the normalization layer with the convolution layer to reduce arithmetic complexity, and adding a new DLQ layer to keep the bit size small while maintaining the accuracy. Based on the experimental results, our proposed design manages to achieve a frame rate of 8.3 FPS with the throughput of 31.5 GOPS, outperforming the same convolution computation that is performed by Ryzen 5 3600 CPU up to $69.3\times $ in latency. Moreover, our proposed design also has the smallest clock cycle ratio up to $1.75\times $ than other commercial accelerators. The system is useful and suitable for edge computing applications.

With recent development in internet speed and reliability, cloud computing has become a more reliable solution for the user. In many cases where data privacy is critical, fully homomorphic encryption (FHE) can be a security solution for securing cloud computing. FHE enables computation on encrypted data, hence it ensures data privacy in case of cloud computing. One popular scheme of FHE is the BFV homomorphic encryption scheme, which is based on ring learning with error (RLWE) computation. The BFV scheme uses ring polynomials as the main object, hence its encryption, decryption, and evaluation require high-degree polynomial multiplication. In this paper, we present comprehensive design and implementation of a hardware architecture to accelerate encryption and decryption in BFV scheme. Our accelerator uses convolution approach for calculating a polynomial multiplication. To implement the convolution, we use a systolic array to calculate polynomial convolution followed by a simple delayed subtraction to calculate polynomial modulo reduction inside our accelerator’s core. Moreover, we use a built-in Gaussian pseudo-random number generator (PRNG) to generate Gaussian noise in the encryption operations. Finally, we implement the 1024 degrees BFV accelerator on the Xilinx PYNQ Z1 board and compare the encryption and decryption performances to other methods as well as a software implementation on Intel Core i7 with 8GB memory. Experimental results show that our accelerator outperforms the clock cycles of other methods with the same polynomial degrees 1024 up to $22\times $ . Moreover, our proposed Gaussian PRNG has better $2\times $ correlation compared to the rotation-only-based PRNG. Finally, our accelerator accelerates up to $9\times $ for encryption and $3.5\times $ for decryption as well as $6.8\times $ for overall compared to Microsoft SEAL on Intel Core i7 processor with 8GB memory. The proposed design is scalable for higher degrees polynomial multiplication and useful for security technology such as high-speed secure cloud computing, blind computing, and secure communication.

This article proposes a scalable accelerator for deep learning (DL) implementation on edge computing, which is often limited by power, storage, and computation speed. The accelerator is based on systolic array cores with 126 processing elements (PEs) and optimized for YOLOv3-Tiny with $448\times448$ input images. Two multicast (MC) network architectures, feature map multicasting and weight multicasting, are introduced to control data stream distribution within the multicores. Results show that the proposed weight multicast (W-MC) systems outperformed the feature map multicast (FMAP-MC) systems in multicore scenarios, with up to $2.23\times $ frame rates per second (FPS). The 4-core W-MC system achieved the best efficiency with an overall frame rate of 13.73 FPS/W and an overall throughput of 35.83 GOPS/W. The 8-core W-MC system delivered the best performance, with a frame rate of 38.50 FPS after normalization to the standard YOLOv3-Tiny network. The proposed accelerator offers better computational efficiency and greater accelerator utilization in real-world inference scenarios, compared to previous state-of-the-art works.

Arrhythmia is a heart disorder in which the heart beats irregularly. Electrocardiogram (ECG) has been widely used as a tool for detecting arrhythmias although the interpretation of ECG recordings is still tedious, time-consuming, and become a difficult task since it needs beat-by-beat manual examination. In arrhythmia classification studies, the inter-patient method is required to obtain unbiased results and has been used in most studies to detect arrhythmias specifically in large classes, such as normal, ventricular, atrial, and fusion beats. However, this method is still limited to use in detecting more specific arrhythmias, particularly in morphological arrhythmias, such as bundle branch block and premature beats. In addition, the methods usually only use one ECG lead. To overcome this limitation, in this work, we propose inter-patient-based arrhythmias classification using combined two ECG leads automatically by employing machine learning methods, specifically ensemble learning. The classification is intended to detect 5 classes of morphological arrhythmia which are Left Bundle Branch Block (LBBB), Left Right Branch Block (RBBB), Premature Ventricular Contractions (PVC), Premature Atrial Contractions (PAC), and Normal. This work also details the method covering data set preparation, algorithm and design parameters exploration for pre-processing ECG signals, features extraction and selection, and hyper parameter tuning for employed machine learning methods. Evaluation results show that the proposed machine learning method, which is Ensemble Learning achieves performance improvements, compared to similar other works with average results of accuracy 87%, recall 87.4%, precision 88.4%, and F1-score 87%. These results correspond to performance improvements compare to state of the art methods for about 12% of accuracy, 28% of recall and 24% of precision, respectively. Furthermore, the proposed work potentially can be employed in real-world clinical practice, specifically as fast yet accurate aided tool for cardiac events diagnostic.

Fish is one of the most demanding protein sources in the food industry. However, the increasing demand must be followed by increasing production efficiency. One of the problems in fish production efficiency is an ineffective feeding method. In this paper, we address the problem of fish feeders using artificial intelligence in an aquarium. We propose fish appetite detection using multi-modal sensors resulting in the data for our AI system. Our AI system consists of R(2+1)D convolutional layers and dense networks to process video and accelerometer data. The video data is split into 20 frames and processed by an R(2+1)D convolutional neural network. The accelerometer data is used to train several networks such as 1-dimensional CNN, GRU, and dense (ANN). The system is implemented in an aquarium with two sensors i.e., a webcam camera and an accelerometer and a main board processing using Raspberry-Pi 4. Experimental results show that the proposed system outperforms other methods with validation accuracy up to 99.09% for the Zeromean dense model and up to 99.39% for the Filtered dense model. The work is useful for automation and efficiency in aquaculture.