In this study, we propose a real-time pedestrian detection system using a FPGA with a digital image sensor. Comparing with some prior works, the proposed implementation realizes both the histogram of oriented gradients (HOG) and the trained support vector machine (SVM) classification on a FPGA. Moreover, the implementation does not use any external memory or processors to assist the implementation. Although the implementation implements both the HOG algorithm and the SVM classification in hardware without using any external memory modules and processors, the proposed implementation’s resource utilization of the FPGA is lower than most of the prior art. The main reasons resulting in the lower resource usage are: (1) simplification in the Getting Bin sub-module; (2) distributed writing and two shift registers in the Cell Histogram Generation sub-module; (3) reuse of each sum of the cell histogram in the Block Histogram Normalization sub-module; and (4) regarding a window of the SVM classification as 105 blocks of the SVM classification. Moreover, compared to Dalal and Triggs’s pure software HOG implementation, the proposed implementation‘s average detection rate is just about 4.05% less, but can achieve a much higher frame rate.

This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction flows, each of which performs fixed operational functions to create a 256-bit long instruction format. However, one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of dedicated compilers. Developing an architecture-specific compiler is really challenging. An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format. This scheduler is used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture is organized into six main stages, namely, fetch, instruction scheduler, decode, execute, data memory, and writeback. The complete design is verified, synthesized, and implemented on a Xilinx Virtex-6 (xc6vlx240t-1-ff1156). Maximum synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per cycle value that outperforms that of existing open-source RISC-V cores.

This article proposes a scalable accelerator for deep learning (DL) implementation on edge computing, which is often limited by power, storage, and computation speed. The accelerator is based on systolic array cores with 126 processing elements (PEs) and optimized for YOLOv3-Tiny with $448\times448$ input images. Two multicast (MC) network architectures, feature map multicasting and weight multicasting, are introduced to control data stream distribution within the multicores. Results show that the proposed weight multicast (W-MC) systems outperformed the feature map multicast (FMAP-MC) systems in multicore scenarios, with up to $2.23\times $ frame rates per second (FPS). The 4-core W-MC system achieved the best efficiency with an overall frame rate of 13.73 FPS/W and an overall throughput of 35.83 GOPS/W. The 8-core W-MC system delivered the best performance, with a frame rate of 38.50 FPS after normalization to the standard YOLOv3-Tiny network. The proposed accelerator offers better computational efficiency and greater accelerator utilization in real-world inference scenarios, compared to previous state-of-the-art works.