We describe 100 nm gate length PD-SOI transistors with the best SOI I/sub on/-I/sub off/ characteristics reported for the 0.18 /spl mu/m technology generation. SOI inverter delay is 7.4 ps at Vdd=1.5 V and L/sub gate/=100 nm. Inverter delays show 16% (fanout=1) and 8% Vdd(V) (fanout=4) improvement over comparable bulk CMOS. Scaling analysis for PD-SOI shows a reduced role for junction capacitance and an increased history effect for scaled devices, so that SOI has significantly diminished performance gain relative to bulk CMOS for 50 nm devices (0.1 /spl mu/m generation).
1 October 2023 in Interaction Design and Architecture(s)
The use of hybrid educational environments, especially after COVID-19 pandemic, has intensified leading to new pedagogic challenges as the integration of biometric sensors into learning processes. Instructors must adapt their methods so that teaching and its quality are not negatively affected. The aim of this study is to enhance the understanding of students’ learning experiences by analysing biometric data during different learning activities. This paper focuses on the use of an Internet of Things (IoT) device, to collect Galvanic Skin Response (GSR) and Heart rate (HR) levels, in addition to biometric data. The quantitative analysis of the collected data shows a correlation between the data extracted that allow us to detect changes on students’ emotions. Subsequently the data analysis is used by instructors to provide formative feedback to enhance student learning, benefiting learners in terms of self-directed learning and motivation which can help them to improve their performance. The paper illustrates a case study of a hybrid learning university learning activity adopted in undergraduate programmes.