Single LiNbO₃ (LNO) crystals are widely utilized in surface acoustic wave devices, optoelectronic devices, and novel ferroelectric memory devices due to their remarkable electro-optic and piezoelectric properties, and high saturation and remnant polarizations. However, challenges remain regarding their nanofabrication that hinder their applications. The prevailing etching techniques for LNO encompass dry etching, wet etching, and focused-ion-beam etching, each having distinct merits and demerits. Achieving higher etching rates and improved sidewall angles presents a challenge in LNO nanofabrication. Building upon the current etching researches, this study explores various etching methods using instruments capable of generating diverse plasma densities, such as dry etching in reactive ion etching (RIE) and inductively coupled plasma (ICP), proton exchange-enhanced etching, and wet chemical etching following high-temperature reduction treatment, as well as hybrid dry and wet etching. Ultimately, after employing RIE dry etching combined with wet etching, following a high-temperature reduction treatment, an etching rate of 10 nm/min and pretty 90° sidewall angles were achieved. Furthermore, high etching rates of 79 nm/min with steep sidewall angles of 83° were obtained using ICP dry etching. Additionally, using SiO₂ masks, a high etching rate of 108 nm/min and an etching selectivity ratio of 0.86:1 were achieved. Distinct etching conditions yielded diverse yet exceptional results, providing multiple processing paths of etching for the versatile application of LNO.

Piezoelectric-actuated machine tools (PAMTs) exhibit nanoscale motion capabilities, with their S-shaped curve trajectory further enabling smooth path execution and reduced terminal pulse. However, the speed changes inherent in multi-order trajectories introduce an additional non-uniform creep difference (NCD), which differs significantly from conventional hysteresis effects. Traditional models are inadequate for addressing this mixed shape nonlinearity. To overcome this limitation, this paper proposes a hybrid compensation method for the S-shaped curve trajectory of piezoelectric-actuated machine tools. The general deformation law is first established through a comprehensive mechanism analysis. The NCD and hysteresis, induced by speed changes and inherent properties, are decoupled and addressed using a pre-known phenomenon model and a clockwise operator model, respectively. Finally, a hybrid feedforward control strategy is developed to integrate these models for effective compensation. Experimental results demonstrate that the hybrid compensation method achieves a maximum relative error of 5.48% and a maximum mean square error of 0.28%, effectively mitigating the dual nonlinear factors arising from the piezoelectric-actuated machine tool’s trajectory in feedforward control.

The interfacial layers appearing in low-dimensional ferroelectric devices due to polarization fluctuations near electrodes could destabilize spontaneous polarizations and reduce dielectric permittivity significantly. But they can conversely work as embedded selectors in high-density ferroelectric LiNbO3 crossbar memories when the interfacial domains are volatile. In contrast, the digital data stored in the nearby intrinsic domains are nonvolatile. The stored data can be nondestructively read out through on/off currents following through erasable conducting domain walls between two antiparallel/parallel domains. However, the intrinsic physics how to adjust the onset voltage of the selector is still unclear. Here, we fabricated the mesa-like cell in contact with two side electrodes at the surface of a monodomain LiNbO3 single crystal and found the selection functionality of the interfacial layer near the head of the pristine domain. The onset voltage of the selector proportional to the interfacial-layer thickness can be continuously modulated by the tilted angle of the electrode projected along the domain orientation, unlike the electrode in the tail that cannot change the onset voltage. It is believed that the volatile domain within the interfacial layer arises from an imprint field built up by trapped electrons in compensation of the opposite domain boundary charge near the head. The designed electrode geometry provides guidance to integrate the high-density LiNbO3 crossbar memory.

Multilevel memristors are being developed for neuromorphic computing to overcome von Neumann architecture limitations, requiring atomic-scale scalability, high-speed operation, and energy-efficient reliability. Erasable conducting ferroelectric domain walls show unique functionality beyond bulk materials, enabling nanoscale multilevel information storage. In this study, the principle of a multilevel domain wall memory device is proposed using a LiNbO3 single-crystal film in atomistic smoothness integrated with the Si wafer after inhibiting the wall sideways motion within a step-like LiNbO3 cell in contact to two side electrodes. The confined domain switching within each step enables the programming of three distinct resistance states, in exhibition of conceptional multi-state memory at nanoscale. Efficient image convolution was performed through the construction of 3×3 arrays of the memory cells which served as a convolution kernel to enable rapid feature extraction, highlighting the potential of multilevel domain wall memory as a promising platform for the rapid expansion of deep learning.

Lithium niobate ferroelectric domain wall memory is promising for applications in digital economy, AI and computing, yet the high coercive field of the domain affiliated with an interfacial layer to function as an embedded selector in a high onset voltage hinders the shrinkage of the cell. Here, we fabricated a LiNbO ₃ domain wall mesa in contact with two side W electrodes via a chemical mechanical polishing technique compatible with the CMOS backend-of-line process. By introducing an IGZO intermediate layer between W and LiNbO ₃ , the coercive field was reduced from 690 to 306 , and low-frequency ferroelectric hysteresis loops become more symmetric by suppressing an imprint effect. The memory operation time is as short as 20 ns, where the binary data can be read out through erasable conducting domain walls in an on/off ratio of 10 ⁴ and retention time of 10 ⁵ s, providing a viable route for low-voltage and high-stable LiNbO ₃ memory integration.