Synthetic aperture radar (SAR) is a well-known imaging technique and most commonly used up to the microwave frequency spectrum (below 30 GHz) which provides spatial resolution in the sub-m range. To enhance the resolution, higher frequency spectra such as millimeter-wave (mmWave) and terahertz (THz) regions are being investigated. The mmWave and THz spectral ranges extend the SAR applications to non-destructive testing (NDT), material characterization, and sub-mm resolution imaging. However, the higher frequency spectrum suffers from higher path loss and potentially higher atmospheric absorption that limits the propagation distance. Nevertheless, the mmWave/THz spectrum is suitable for short-range applications such as indoor room profiling. From theoretical analysis, it can be summarized that the higher frequency spectrum provides better resolution but a comparative study on the impact on the image quality of the frequency spectrum ranging from GHz to THz has not been presented. Besides, as of the hardware complexity of the THz devices, the optimum range of the spectrum is always under investigation. The optimum range is defined where no strong improvements in the image quality are achievable with further increases in the frequency spectrum. Therefore, this paper presents an overview of electronics-based imaging using the SAR technique for the frequency spectrum ranging from GHz to THz with the focus on NDT and high-resolution imaging. Seven frequency bands: 5-10 GHz, 68-92 GHz, 75-110 GHz, 0.122-0.168 THz, 0.22-0.33 THz, 0.325-0.5 THz, and 0.85-1.1 THz are selected for a comparative analysis. The results are presented for 2D and 3D imaging using the backprojection algorithm. Additionally, state-of-the-art imaging based on SAR technique with electronics transceiver modules has only been demonstrated up to the sub-0.75 THz, whereas in this paper the spectrum up to 1.1 THz has been addressed.

In radar remote sensing, the Terahertz (THz) spectrum is presently being investigated worldwide with focus on short-range indoor and outdoor applications. The spectrum broadens the unmanned aerial vehicle (UAV) based synthetic aperture radar (SAR) applications to indoor room profiling with sub-mm resolution and material characterization as many materials have unique fingerprints at this spectrum. SAR technique requires precise localization information of the mobile radar sensor, which in conventional SAR is achieved using an existing localization infrastructure, such as a global positioning system (GPS) and inertial measurement unit (IMU). For the indoor THz SAR, the GPS does not provide coverage in indoor complex environments, and also the state-of-art compact IMU does not provide the required sub-mm accuracy. These limitations can be overcome by utilizing an indoor localization system. Therefore, this paper presents an indoor THz simultaneous localization and mapping (SLAM) system. The system comprises of passive tags based radio frequency identification (RFID) localization system and SAR that provides the UAV localization and mapping of the in-room objects. Another challenge for the UAV based indoor THz SAR that is addressed in this paper is motion compensation (MOCO). At the THz, MOCO requires special consideration due to very small trajectory deviation is in the range of carrier wavelength. Therefore, to study the effects of the sub-mm translational errors, a testbed has been set up, and measurement results are presented in this paper along with the 3D electromagnetic simulation results for a carrier frequency of 275 GHz and bandwidth of 50 GHz. Further, to compensate these errors, the sub-mm localization system is used and the results are presented to validate the proposed solution for indoor THz SAR MOCO.

Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for $8\times 32$ -bit tiles and 316 MOPS for $8\times 64$ -bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.

In recent years, Convolutional Neural Network CNN have been incorporated in a large number of applications, including multimedia retrieval and image classification. However, CNN based algorithms are computationally and resource intensive and therefore difficult to be used in embedded systems. FPGA based accelerators are becoming more and more popular in research and industry due to their flexibility and energy efficiency. However, the available resources and the size of the on-chip memory can limit the performance of the FPGA accelerator for CNN. This work proposes an High-Level Synthesis HLS library for CNN algorithms. It contains seven different streaming-capable CNN (plus two conversion) functions for creating large neural networks with deep pipelines. The different functions have many parameter settings (e.g. for resolution, feature maps, data types, kernel size, parallelilization, accuracy, etc.), which also enable compile-time optimizations. Our functions are integrated into the HiFlipVX library, which is an open source HLS FPGA library for image processing and object detection. This offers the possibility to implement different types of computer vision applications with one library. Due to the various configuration and parallelization possibilities of the library functions, it is possible to implement a high-performance, scalable and resource-efficient system, as our evaluation of the MobileNets algorithm shows.