A miniaturized D-band frequency sixtupler using a mode analysis of the harmonics is proposed to improve the output power of the CMOS process using a low driving signal. The operation mode of the harmonics in a differential frequency multiplier is analyzed to independently control the behavior at odd-and even-order harmonics. The proposed CMOS sixtupler consists of a tripler, a buffer amplifier, a push–push doubler, and impedance matching networks. The interstage network between the tripler and the buffer amplifier performs impedance matching of the desired frequency and filtering of unwanted signals. The network between the buffer and the doubler simultaneously performs impedance matching while acting as the harmonic reflector. The output power of the doubler located at the final stage of the sixtupler is improved by LC source degeneration, providing LC resonance, and a high impedance condition at the second-harmonic frequency. The proposed sixtupler was implemented in an area of 0.4 mm $^{2}$ using the 65-nm CMOS technology. The measurement results indicate a saturated power of $-$ 1.2 dBm with a harmonic rejection ratio (HRR) of 25 dBc for an input driving power of 15.5 dBm at 148.2 GHz. The maximum conversion gain (CG) is $-$ 0.7 dB at a low driving power of $-$ 6.5 dBm at 150.6 GHz.

A V-band CMOS frequency tripler with efficient input-output, and interstage matching networks is proposed to improve the output power and conversion efficiency. The interstage matching network, located between a tripler-core and a buffer amplifier, simultaneously performs the impedance matching of a desired third harmonic signal and the filtering of unwanted fundamental and even harmonic signals, without an additional power loss in a small area. Wideband operation and differential signal balance characteristics are achieved at the input and output by using a transformer-based balun with a compensation capacitor. The proposed tripler was implemented in a size of 0.476 mm ² using the TSMC 65-nm CMOS technology. Measurement results show a saturated output power of 6.4 dBm with a harmonic rejection of 37 dBc for an input power of 10 dBm at 59.4 GHz. The maximum conversion efficiency is 3.92% with an input power of 6.5 dBm at 59.4 GHz.

A method of measuring the amplitude ratios and phase differences among the same RF output signals from multiple ports at the same frequency is proposed. A power combining module is used to couple multiple signals vectorially from the ports. In the proposed method, the amplitude ratios among RF signals from multiple ports are calculated by using the output power of the module to which only one port is connected, and by using the S-parameters of the module itself. However, the phase differences among multiple ports cannot be simply represented by the differences between the output power of the module and the ideally combined power, because the impedances of all ports except measuring ports should be perfectly matched. The proposed method uses a parameter that compensates for the impedance mismatches generated at the other ports to achieve precise measurement of the phase differences among multiple ports. Measurement results using the passive component with three ports reveal that the mean errors of the proposed method are 1.272.15: in the amplitude and phase, respectively, as compared with measurements using the vector network analyzer. The standard deviations of the errors show 1.69% and 1.68° in the amplitude and phase, respectively.

A CMOS two-way differential power divider is proposed to reduce the insertion loss (IL) and size in the $D$ -band. The power distribution is achieved using a low-loss differential power divider with a capacitive loading structure, without modifying the matching network of the unit devices. In addition, the degradation of the IL due to the parasitic inductance of groundings is made negligible by using the virtual ground of the differential structure. The impedance of the differential-mode transmission line (TL), which is half that of the single-ended line, is designed in the impedance range achievable in the bulk CMOS process, utilizing capacitive loading techniques. The 3-D electromagnetic (EM) simulation results of a two-way power divider show a low IL within 0.35 dB at 110–170 GHz. The proposed power divider achieves a measured minimum IL of 0.32 dB at 160 GHz with a core size of 0.0075 mm $^{2}$ .

In this article, a highly efficient power module is presented with two class-E power amplifiers and an adaptive power combiner for transmitting output powers >100 W at 6.78 MHz in a wireless power transfer system. The losses caused by the combiners and interstage matching circuits or mismatching between the amplifier, and the combiners can significantly reduce the overall efficiency of the power module. To achieve an efficient combination of the output amplifier signals, the adaptive power combiner is proposed based on the consideration of the optimum load impedance characteristics of the power amplifiers. The input impedance of the combiner is designed using series capacitors and resistors between the two input ports of the combiner and the two output signals of the class-E amplifiers at the optimum load condition. The output performances of the proposed module can decrease based on the component mismatch between the two power amplifiers. The proposed power module was implemented on an FR4 PCB, with a 15 mm metal heat sink, and demonstrated an output power of 123.3 W, a power-added efficiency of 85.7%, and a power gain of 25.6 dB at 6.78 MHz. The second harmonic suppression of the module was 37 dBc.

A D-band phase shifter for CMOS transmitters in a millimeter-wave imaging system is proposed based on vector modulator configuration. Depending on the phase control biasing, the output impedance variation of phase shifters at the millimeter-wave transmitter can interfere with optimizing the operation of power amplifiers with a fixed input impedance. The proposed phase shifter incorporates an output-matching circuit with transformers to minimize output impedance variations. Differential I and Q channels are coupled in each transformer and combined at the power combiner. This configuration can minimize the impedance variation at the output port and increase the saturated output power of the proposed phase shifter. The proposed phase shifter, implemented on 0.184 mm2 using a 65-nm CMOS process, exhibits a maximum gain of -11 dB, a phase shift of over 180°, and an input-referred P1dB of 7 dBm in the frequency bandwidth of 115−135 GHz. Th e total current consumption is a maximum of 36 mA at a supply voltage of 1.2 V.