Multilevel inverters are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single phase cascaded multilevel inverter topology is suggested in this paper. The proposed multilevel inverter topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity, while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable multilevel inverter topologies to prove the superiority of the proposed structure. Selective harmonic elimination (SHE) pulse width modulation (PWM) technique is used to produce the pulses for switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and the cascading of two such units to achieve 71 levels at the output.

Multilevel Inverters are a new family of converters for dc-ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology which consist of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in the paper to demonstrate the features of the proposed topologies. Finally, several experimental results have been included in the paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes.

Multilevel inverter (MLI) topologies play a crucial role in the dc-ac power conversion due to their high-quality performance and efficiency. This article aims to propose a new switched-capacitor-based boost multilevel inverter topology (SCMLI). The proposed topology consists of nine power semiconductor switches with one dc voltage source and two capacitors, capable of generating a nine-level output voltage waveform with twice voltage gain. With the addition of two switches, the proposed topology can be used for higher voltage-gain applications. Other features of the proposed topology include the self-voltage balancing of the capacitors, parallel operation of the capacitors, lower voltage stress across the switches, along with the inherent polarity changing capability. To obtain the high-quality output waveform, a selective harmonic elimination pulsewidth modulation technique is applied. In this technique, the detrimental low-order harmonics can easily be regulated and eliminated from the output voltage of MLI. The proposed topology is compared with the recently introduced SCMLI topologies considering various parameters to set the benchmark of the proposed topology. The performance of the proposed MLI is investigated through various experimental results using a laboratory prototype setup.

In this article, a hybrid asynchronous particle swarm optimization-genetic algorithm (APSO-GA) is proposed for the removal of unwanted lower order harmonics in the cascaded H-bridge multilevel inverter (MLI). The APSO-GA is applicable to all levels of MLI. In the proposed method, ring topology based APSO is hybrid with GA. APSO is applied for exploration and GA is used for the exploitation of the best solutions. In this article, optimized switching angles are calculated using APSO-GA for seven-level and nine-level inverter, and results are compared with GA, PSO, APSO, bee algorithm (BA), differential evolution (DE), synchronous PSO, and teaching–learning-based optimization (TLBO). Simulation results show that APSO-GA can easily find feasible solutions particularly when the number of switching angles is high; however, the rest of all stuck at local minima due to less exploration capability. Also, the APSO-GA is less computational complex than GA, BA, TLBO, and DE algorithms. Experimentally, the performance of APSO-GA is validated on a single-phase seven-level inverter.

This study presents selective harmonic elimination pulse width modulation technique‐based hybrid asynchronous PSO‐Newton‐Raphson (APSO‐NR) algorithm for the elimination of undesired harmonics in cascaded H‐bridge multilevel inverter. The proposed algorithm is applicable to all levels of MLI having equal and non‐equal DC sources. In the proposed method, ring topology‐based APSO algorithm is hybrid with NR method. APSO worked as a global search technique and NR is used for the refinement of best solutions. APSO‐NR is applied to the seven‐level inverter to eliminate fifth and seventh harmonics. In simulations, the performance of the proposed algorithm is compared with genetic algorithm, bee algorithm and particle swarm optimisation. The results proved that the proposed algorithm is efficient, and gives more precise firing angles in less number of iterations with high capability of tackling local optima. For the 48% of modulation index range, APSO‐NR minimised the fitness function value lower than (10 ⁻²⁵ ). The proposed algorithm is validated through the experimental implementation of the three‐phase seven‐level inverter.