Multilevel inverters are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single phase cascaded multilevel inverter topology is suggested in this paper. The proposed multilevel inverter topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity, while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable multilevel inverter topologies to prove the superiority of the proposed structure. Selective harmonic elimination (SHE) pulse width modulation (PWM) technique is used to produce the pulses for switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and the cascading of two such units to achieve 71 levels at the output.

Multilevel Inverters are a new family of converters for dc-ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology which consist of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in the paper to demonstrate the features of the proposed topologies. Finally, several experimental results have been included in the paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes.

Multilevel inverter (MLI) topologies play a crucial role in the dc-ac power conversion due to their high-quality performance and efficiency. This article aims to propose a new switched-capacitor-based boost multilevel inverter topology (SCMLI). The proposed topology consists of nine power semiconductor switches with one dc voltage source and two capacitors, capable of generating a nine-level output voltage waveform with twice voltage gain. With the addition of two switches, the proposed topology can be used for higher voltage-gain applications. Other features of the proposed topology include the self-voltage balancing of the capacitors, parallel operation of the capacitors, lower voltage stress across the switches, along with the inherent polarity changing capability. To obtain the high-quality output waveform, a selective harmonic elimination pulsewidth modulation technique is applied. In this technique, the detrimental low-order harmonics can easily be regulated and eliminated from the output voltage of MLI. The proposed topology is compared with the recently introduced SCMLI topologies considering various parameters to set the benchmark of the proposed topology. The performance of the proposed MLI is investigated through various experimental results using a laboratory prototype setup.

In this article, a hybrid asynchronous particle swarm optimization-genetic algorithm (APSO-GA) is proposed for the removal of unwanted lower order harmonics in the cascaded H-bridge multilevel inverter (MLI). The APSO-GA is applicable to all levels of MLI. In the proposed method, ring topology based APSO is hybrid with GA. APSO is applied for exploration and GA is used for the exploitation of the best solutions. In this article, optimized switching angles are calculated using APSO-GA for seven-level and nine-level inverter, and results are compared with GA, PSO, APSO, bee algorithm (BA), differential evolution (DE), synchronous PSO, and teaching–learning-based optimization (TLBO). Simulation results show that APSO-GA can easily find feasible solutions particularly when the number of switching angles is high; however, the rest of all stuck at local minima due to less exploration capability. Also, the APSO-GA is less computational complex than GA, BA, TLBO, and DE algorithms. Experimentally, the performance of APSO-GA is validated on a single-phase seven-level inverter.

In this paper, a new switched capacitor based multilevel inverter topology is proposed. The proposed topology generates seven level (7L) output voltage using a single dc voltage source along with two floating capacitors. The output voltage of the proposed topology is three-times higher than the input voltage (i.e., gain factor of Vin:Vout = 1:3) along with self-voltage balancing of capacitors. The proposed seven level triple voltage gain boost inverter (7L-3GBI) inherently generates a bipolar waveform without backend H-bridge that reduces the total standing voltage of the topology. The practicability of the proposed topology has been demonstrated by having a quantitative and cost comparison with similar topologies. Furthermore, the workability of the proposed 7L topology has been validated through different results taken from a prototype laboratory setup.

Multilevel inverters (MLI) since its inception have caught the attention of researchers for medium and high power application. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 level at the output with three dc voltage sources and eight switches. Three extention of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, results in maximum efficiency of 98.5%. Nearest level control (NLC) pulse width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to shows the feasibility of the proposed MLI topology.