This paper describes a V-Band power detector fabricated in a BiCMOS 55nm (f _t /f _max = 320GHz/370GHz) process. The detector is to be used in millimeter-wave circuits for automatic level control, built-in test and in-situ power measurement. The detector occupies an area of 0.0064mm ² and exhibits an equivalent input resistance/capacitance of 1kΩ /13fF around 60GHz. Measurements show a detection dynamic range of 30dB over the 50GHz to 66GHz bandwidth. The minimum detectable input power is -22dBm thanks to the use of common base bipolar SiGe transistor at the input stage. The measured output bandwidth is 700MHz. In nominal bias conditions, the detector power consumption is 90μW for -22dBm input power and it increases to 800μW for 8.5dBm input power. These performances are beyond the current state-of-the-art.

A single-stage 60GHz class-A bipolar power amplifier (PA) is fabricated in a BiCMOS 55nm technology. In order to enhance the power added efficiency (PAE) behavior of the PA, a bias control loop, based on direct power detection, is implemented in order to dynamically adjust the DC bias current of the PA according to its output power level. A power detector (PD) is connected directly at the output of the amplifier in order to track the envelope variation of its output signal. The employed PD has a dynamic range of more than 30dB, and a maximum power consumption of 0.8mW. Under constant bias conditions, the PA has a power gain of around 7dB, a maximum PAE of 16%, and an output compression point of around 7.5dBm while driving 25.8mA under 1.2V supply voltage. Under adaptive bias control, the mean value of the DC current is reduced down to 20.8mA, while maintaining high power gain, leading to a significant enhancement of the PAE over the linear input dynamic range of the PA. System level simulations show that the applied technique enhances the average PAE and DC power consumption by 18% without significant discrepancies on the EVM, ACPR, and power gain.

In this work, a new combiner analysis method for the design of Doherty Power Amplifiers (DPA) is proposed. A compact L-C combiner is used to validate the proposed method through both simulation and realization of a two-stage DPA in a 130nm RF-SOI process. Using a 2.3GHz CW signal, the PA achieves a measured peak PAE of 51% at 32dBm output power under 3.4V supply voltage. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at -35dBc E-UTRA ACLR when using a 10MHz-50RB QPSK LTE uplink signal with memoryless DPD. At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively.

This paper extends the quasi-load insensitive (QLI) Class-E Doherty power amplifier (PA) design methodology to address Doherty PA combiners with complex load impedance trajectories. Additionally, the QLI operation is analyzed for generalized class-E output matching networks with input series inductors and finite DC-feed inductors. We demonstrate that the QLI class-E Doherty operation can be achieved for various Doherty combiners by selecting the appropriate combination of class-E outputs matching network resonance factors and input series inductances. Moreover, a modified class-E output network is proposed to overcome the frequency limitation that might be caused by the class-E network resonance factor choice. To validate the proposed methodology, two 40 W Doherty PAs are designed and simulated using commercial GaN HEMT transistors achieving more than 70% efficiency over a 6 dB output power back-off at 3.8 GHz.