An accurate de-embedding method for millimeter-wave and sub-millimeter-wave integrated circuits is presented. In this “Half-Thru” de-embedding method, the pad-interconnects parasitics effects are modeled as a Half-Thru structure from both parts of the device under test. Several de-embedding methods over millimeter and sub-millimeter wave frequencies are compared in integrated technology by considering S-CPW transmission lines as device under test. From these comparisons we propose an effective way to de-embed transmission lines. The S-CPW transmission line model and results are obtained from full-wave electromagnetic simulations in BiCMOS 55-nm technology.

This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ( $\mathrm {P}_{\mathrm {DC}}$ ), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs $\ge80$ GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ( $\mathrm {P}_{\mathrm {DC}}$ ) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per $\mathrm {P}_{\mathrm {DC}}$ ( ${\mathrm {GBP}} \mathord {\left /{ {\vphantom {{\mathrm {GBP}} \mathrm {P}_{\mathrm {DC}}}} }\right. } \mathrm {P}_{\mathrm {DC}}$ ) of 6.01 GHz/mW while being power-efficient.

This letter presents a stacked parallel plate (SPP) shunt capacitor (SC) that benefits from metal stack increment with process nodes advancement. It demonstrated high quality (Q) factor and high self-resonance frequency (SRF), promoting the design of analog integrated circuits (IC) in low-cost highly-integrated CMOS technologies at millimeter-wave (mm-wave) frequency range. As a proof-of-concept, an analytical-equation based design method is also proposed and three ac-grounded capacitors: 300-fF, 600-fF and 900-fF, are implemented in STMicroelectronics (STM) 55-nm process. Characterization is performed up to 100 GHz. An effective capacitance density of 0.8 fF/μm2 is obtained. Measurements show Q-values reaching up to 14.7 at 100 GHz and equivalent input series resistances with flat wide band behavior reaching at most an average of 0.55 Ω. SRFs of 140 GHz for the 900-fF SPP-SC up to 368 GHz for the 300-fF SPP-SC are also determined from measurements: the highest SRFs for such large capacitances to the authors’ knowledge.

Summary form only given, as follows. Electrostatic discharge protection is a must in every integrated circuit. At microwave frequencies, the influence the protection devices have over the circuit they protect can significantly impact the functioning of the latter. A model for the SCR (silicon controlled rectifier) and the ESD protection diode was developed. Its purpose is to estimate this influence at frequencies up to 65 GHz. A complex device, the DTSCR (diode triggered SCR) is used to demonstrate the consistency of the models.

This paper extends the quasi-load insensitive (QLI) Class-E Doherty power amplifier (PA) design methodology to address Doherty PA combiners with complex load impedance trajectories. Additionally, the QLI operation is analyzed for generalized class-E output matching networks with input series inductors and finite DC-feed inductors. We demonstrate that the QLI class-E Doherty operation can be achieved for various Doherty combiners by selecting the appropriate combination of class-E outputs matching network resonance factors and input series inductances. Moreover, a modified class-E output network is proposed to overcome the frequency limitation that might be caused by the class-E network resonance factor choice. To validate the proposed methodology, two 40 W Doherty PAs are designed and simulated using commercial GaN HEMT transistors achieving more than 70% efficiency over a 6 dB output power back-off at 3.8 GHz.