Energy saving and system reliability are two crucial issues for designing modern multiprocessor systems. There has been reliability-aware power management with dynamic voltage–frequency scaling (DVFS) schemes in recent studies. However, they are limited to optimization under the impact of DVFS on energy and reliability and have not considered reducing the non-negligible leakage energy consumption. In this paper, we focus on co-management of system reliability and total energy for applications with precedence constrained tasks on heterogeneous multiprocessor real-time systems. We first investigate the impact of energy management techniques on both reliability and energy of the systems using task recovery for fault tolerance and then propose an Energy-efficient Fault-tolerant Scheduling (EFS) scheme integrated with power mode management, which can mitigate the negative impact of DVFS on system reliability. To obtain the optimal energy-efficient reliability-guaranteed scheduling for pre-mapped applications on systems considering various realistic issues, we build mixed integer linear programing formulations with the proposed EFS scheme. To address mapping and scheduling for energy-efficiency and fault-tolerance, we finally develop a framework implemented by a List-based Binary Particle Swarm Optimization algorithm. The extensive comparative evaluations for synthetic and realistic benchmarks show that our approaches outperform several related studies in terms of energy consumption and system reliability.

With the development of industrial networks, the demands for strict timing requirements and high reliability in transmission become more essential, which promote the establishment of a Time-Sensitive Network (TSN). TSN is a set of standards with the intention of extending Ethernet for safety-critical and real-time applications. In general, frame replication is used to achieve fault-tolerance, while the increased load has a negative effect on the schedule synthesis phase. It is necessary to consider schedulability and reliability jointly. In this paper, a heuristic-based routing method is proposed to achieve fault tolerance by spatial redundancy for TSNs containing unreliable links. A cost function is presented to evaluate each routing set, and a heuristic algorithm is applied to find the solution with higher schedulability. Compared to the shortest path routing, our method can improve the reliability and the success rate of no-wait scheduling by 5–15% depending on the scale of topology.

The IEEE 802.1Qbv standard provides deterministic delay and low jitter guarantee for time-critical communication using a precomputed cyclic transmission schedule. Computing such transmission schedule requires routing the flows first, which significantly affects the quality of the schedule. So far off-the-shelf algorithms like load-balanced routing, which minimize the maximum scheduled traffic load (MSTL), have been used to accommodate more time-triggered traffic. However, they do not consider that the bandwidth utilization of periodic flows is decentralized and their criteria for bottleneck of scheduling are imprecise. In this paper, we firstly explore the combinability among different periods of flows, which can measure their ability to share bandwidth without conflict. Then, we propose a novel period-aware routing algorithm to reduce the scheduling bottleneck, thus more flows can be accommodated. The experiment results show that the success rate of scheduling is significantly improved compared to shortest path routing and load balanced routing.

Task mapping has been a hot topic in MPSoC software design for decades. During the mapping process, load balance and communication optimization have been two important performance optimization factors. This paper studies the relations between load balance, inter-processor communications and communication pipeline technique during the mapping process, and proposes an Integer Linear Programming (ILP)-based static task mapping approach, which considers both load balance and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the Task-Processor-Cluster (TP-CLUSTER) algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented ε-constraint (AUGMECON2) method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach.

Deep neural networks have achieved remarkable advancement in various intelligence tasks. However, the massive computation and storage consumption limit applications on resource-constrained devices. While channel pruning has been widely applied to compress models, it is challenging to reach very deep compressions for such a coarse-grained pruning structure without significant performance degradation. In this article, we propose an acceleration-aware fine-grained channel pruning (AFCP) framework for accelerating neural networks, which optimizes trainable gate parameters by estimating residual errors between pruned and original channels with hardware characteristics. Our fine-grained concept consists of both algorithm and structure levels. Different from existing methods that leverage a predefined pruning criterion, AFCP explicitly considers both zero-out and similar criteria for each channel, and adaptively selects the suitable one via residual gate parameters. For structure level, AFCP adopts a fine-grained channel pruning strategy for residual neural networks and a decomposition-based structure, which further extends the pruning optimization space. Moreover, instead of using theoretical computation costs, such as floating-point operations, we propose the hardware predictor that bridges the gap between realistic acceleration and pruning procedure to guide the learning of pruning, which improves the efficiency of model pruning when deployed on accelerators. Extensive evaluation results demonstrate that AFCP outperforms state-of-the-art methods, and achieves a favorable balance between model performance and computation cost.

To ensure that a hardware Trojan remains hidden in a circuit, it is usually necessary to ensure that the trigger signal has a low testability, which has been widely recognized and proven. The most advanced testability-based detection methods are rather slow for large circuits, and the false-positive rate is not as low as that for small circuits. In this paper, a hardware Trojan, through the low testability of the trigger signal and its position characteristics in the circuit, was detected, which greatly improves the detection speed while maintaining a lower false positive rate when being applied to large circuits. First, the Sandia Controllability/Observability Analysis Program (SCOAP) was applied to obtain the 0–1 controllability of the signals in the netlist. Secondly, the controllability value was calculated by the differential amplification model, in order to facilitate K-means clustering to get better results. Then, we calculate the shortest path between each suspicious signal to get the connection between each suspicious signal. Finally, we divide the suspicious signals into several suspicious circuit blocks to screen the real trigger signal. As a result, the false-negative rate of 0% and the highest false-positive rate of 5.02% were obtained on the Trust-Hub benchmarks.