This article presents a low-power, high-resolution, high dynamic range (DR) current-mode direct-to-digital converter (CM-DDC) using a noise-shaping triple-slope quantizer. Both thermal and quantization noises can be first-order shaped out of band, increasing the resolution effectively. High resolution can be realized without using a high sampling rate or high-order shaping architecture. A coarse-fine zoom style quantization is exploited, which reduces the conversion time and, thus, the power consumption of active circuit blocks with dynamic biasing. On the circuit level, a chopped current digital-to-analog converter (DAC) is proposed to reduce 1/ $f$ noise of the current DAC, enhancing the DR. The CM-DDC with light-emitting diode (LED) driver and digital control circuitry is implemented in a standard 55-nm CMOS process and characterized experimentally. The converter achieves a signal-to-noise and distortion-ratio (SNDR) of 94.7 dB and a cross-scale DR of 136.5 dB in 20-Hz bandwidth with 30- $\mu \text{W}$ power for photoplethysmography (PPG)/near-infrared spectroscopy (NIRS) applications. Thanks to the shortened conversion time, the converter’s sampling frequency and signal bandwidth can be adjusted to 200 Hz and 2 kHz, achieving 90.5- and 79.2-dB SNDR, respectively, which allows various current sensing applications. The proposed CM-DDC is also validated with on- body chest PPG measurement.

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance ( Z $_{\mathbf{in}}$ ) boosting. In order to achieve a high Z $_{\mathbf{in}}$ , a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors ( C $_{\mathbf{in}}$ $=$ 0.5 pF, C $_{\mathbf{fb}}$ $=$ 25 fF) are used with a biased pseudo-resistor ( R $=$ 2.5 G $\Omega $ ) fed back to an amplifier internal node. As a result, a high achievable Z $_{\mathbf{in}}$ and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF C $_{\mathbf{amp}}$ is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its Z $_{\mathbf{in}}$ boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/ $\surd$ Hz, and an integrated noise of 0.85 $\mu$ V $_{\mathbf{rms}}$ in 200 Hz band. The Z $_{\mathbf{in}}$ is boosted to 1.92 G $\Omega $ at DC and 1.02 G $\Omega $ at 50 Hz with only 1.0 $\mu$ A in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming 20.3 $\mu$ W in total.

Deep neural networks have achieved remarkable advancement in various intelligence tasks. However, the massive computation and storage consumption limit applications on resource-constrained devices. While channel pruning has been widely applied to compress models, it is challenging to reach very deep compressions for such a coarse-grained pruning structure without significant performance degradation. In this article, we propose an acceleration-aware fine-grained channel pruning (AFCP) framework for accelerating neural networks, which optimizes trainable gate parameters by estimating residual errors between pruned and original channels with hardware characteristics. Our fine-grained concept consists of both algorithm and structure levels. Different from existing methods that leverage a predefined pruning criterion, AFCP explicitly considers both zero-out and similar criteria for each channel, and adaptively selects the suitable one via residual gate parameters. For structure level, AFCP adopts a fine-grained channel pruning strategy for residual neural networks and a decomposition-based structure, which further extends the pruning optimization space. Moreover, instead of using theoretical computation costs, such as floating-point operations, we propose the hardware predictor that bridges the gap between realistic acceleration and pruning procedure to guide the learning of pruning, which improves the efficiency of model pruning when deployed on accelerators. Extensive evaluation results demonstrate that AFCP outperforms state-of-the-art methods, and achieves a favorable balance between model performance and computation cost.

Deep Neural Networks (DNNs) have achieved remarkable success in various Artificial Intelligence applications. Quantization is a critical step in DNNs compression and acceleration for deployment. To further boost DNN execution efficiency, many works explore to leverage the input-dependent redundancy with dynamic quantization for different regions. However, the sensitive regions in the feature map are irregularly distributed, which restricts the real speed up for existing accelerators. To this end, we propose an algorithm-architecture co-design, named Structured Dynamic Precision (SDP). Specifically, we propose a quantization scheme in which the high-order bit part and the low-order bit part of data can be masked independently. And a fixed number of term parts are dynamically selected for computation based on the importance of each term in the group. We also present a hardware design to enable the algorithm efficiently with small overheads, whose inference time mainly scales with the precision proportionally. Evaluation experiments on extensive networks demonstrate that compared to the state-of-the-art dynamic quantization accelerator DRQ, our SDP can achieve 29% performance gain and 51% energy reduction for the same level of model accuracy.

To ensure that a hardware Trojan remains hidden in a circuit, it is usually necessary to ensure that the trigger signal has a low testability, which has been widely recognized and proven. The most advanced testability-based detection methods are rather slow for large circuits, and the false-positive rate is not as low as that for small circuits. In this paper, a hardware Trojan, through the low testability of the trigger signal and its position characteristics in the circuit, was detected, which greatly improves the detection speed while maintaining a lower false positive rate when being applied to large circuits. First, the Sandia Controllability/Observability Analysis Program (SCOAP) was applied to obtain the 0–1 controllability of the signals in the netlist. Secondly, the controllability value was calculated by the differential amplification model, in order to facilitate K-means clustering to get better results. Then, we calculate the shortest path between each suspicious signal to get the connection between each suspicious signal. Finally, we divide the suspicious signals into several suspicious circuit blocks to screen the real trigger signal. As a result, the false-negative rate of 0% and the highest false-positive rate of 5.02% were obtained on the Trust-Hub benchmarks.

Physical Unclonable Functions (PUFs) are significant in building lightweight Internet of Things (IoT) authentication protocols. However, PUFs are susceptible to attacks such as Machine-Learning(ML) modeling and statistical attacks. Researchers have conducted extensive research on the security of PUFs; however, existing PUFs do not always possess good statistical characteristics and few of them can achieve a balance between security and reliability. This article proposes a strong response-feedback PUF based on the Linear Feedback Shift Register (LFSR) and the Arbiter PUF (APUF). This structure not only resists existing ML modeling attacks but also exhibits good Strict Avalanche Criterion (SAC) and Generalized Strict Avalanche Criterion (GSAC). Additionally, we introduce a Two-Level Reliability Improvement (TLRI) method that achieves 95% reliability with less than 35% of the voting times and single-response generation cycles compared to the traditional pure majority voting method.