A review of various proposed schemes to increase the reliability and life span of solid-state lighting (SSL) systems is presented in this article. Since the mainstream devices employed for such lighting systems are inorganic, high-power light-emitting diodes (LEDs), which are devices characterized by their very long life, most of the questions in reliability and endurability arise from the electronic offline circuit driving the LEDs. Issues regarding the limited reliability of specific components, such as electrolytic capacitors, are introduced. Several power-?conversion configurations aimed to capacitance reduction and capacitor technology exchange are put forward as alternative solutions for implementing long-life drivers, with remarks on both their benefits and drawbacks. An extensive literature review on the topic is carried out, and some practical outcomes from recent research on offline LED driving are highlighted.

This paper proposes an offline single-stage light-emitting diode (LED) driver based on a novel approach to reduce low-frequency ripple in LED arrays supplied from mains, while assuring high input power factor (PF). The proposal employs a series resonant dc-dc converter integrated into a bridgeless boost power factor correction (PFC) stage. The resonant stage works to reduce the low-frequency ripple transmitted from the output of the PFC stage to the LEDs with only small power losses. This solution achieves three main goals: 1) reduction of the bulk capacitance used at the dc bus, allowing for the use of long-life film capacitors; 2) increase in the overall efficiency of the LED driver owing to the low switching and conduction losses in the shared switching network; and 3) assuring high input PF. Experimental results of a driver without electrolytic capacitors for a 100-W street lighting LED luminaire are presented, showing overall efficiency in excess of 92%, input PF greater than 0.97, and line current harmonic content in compliance with the IEC 61000-3-2 standard.

In this paper, a static and dynamic photoelectrothermal model including the impact of low-frequency current ripple on light-emitting diodes (LEDs) performance is proposed. The objective of this study is to evaluate the dynamical interaction among thermal, photometrical, and electrical properties of the LEDs when they are supplied by a dc constant current with a superposed low frequency sinusoidal ripple, which is the common case in offline LED drivers. Therefore, this paper presents both a model and experimental data for analyzing the LED photometrical behavior in terms of luminous flux, efficacy, flicker, and chromaticity. Three laboratory prototypes with different heat sinks and LED models have been tested. Experimental results are presented to evaluate the LED photometrical behavior under the aforementioned operating conditions and to validate the proposed modeling methodology.

In this work, a new topology of integrated converter is proposed to be used as an off-line LED driver. The two stages of the converter are made up by a front-end SEPIC power factor corrector and a buck-boost converter for current regulation, both stages sharing the same power switch. It is demonstrated that when both stages work in DCM, less low-frequency ripple is transmitted from the bus capacitor to the output, allowing decreasing the amount of filtering needed and eliminating electrolytic capacitors from the power circuitry. Photometric data is used to size the maximum current ripple permissible at the LEDs, further optimizing filtering requirements and reducing capacitances to the maximum.

This study proposes a novel approach for low-frequency output current ripple minimization in offline light-emitting diode (LED) drivers. This strategy is based on the large-signal modulation of the LED converter duty-cycle so that the output ripple can be reduced and, consequently, the required filtering capacitances of the converter can be somehow decreased. This technique is devised to be used on converters in which a single control loop is employed, such as offline integrated converters, where a single control loop is responsible to control the output current while maintaining the high power factor at the input (mains). The duty-cycle modulation is used to change the shape of the main waveforms of the converter, especially input and output currents. This allows for a reduction of the output current peak-to-peak ripple while the harmonic content of the input current is increased but kept within the limits imposed by the IEC standard. An application example for an integrated two-stage converter based on the cascade connection of two buck-boost converters is shown. Experimental results from a 70-W laboratory prototype supplied from a 115-V grid were carried out and compared with conventional approaches in order to verify the feasibility of the proposed technique.

The aim of this study is to review the state‐of‐the‐art of recent prediction methods for power metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) switching losses using datasheet parameters. A detailed technical literature investigation is carried out to collect the latest research contributions on this subject, pointing out their main features and drawbacks. Then, a particular section is dedicated to compare three different selected methods oriented to Si‐based and SiC‐based MOS power transistors. This analysis is performed on several voltage and current level ratings using an experimental prototype of a double pulse circuit. According to the experimental‐supported study included here, at a particular volt–ampere condition, the Ahmed method provided the lowest theoretical error of 2.38%, while the Guo method attained 41.2% and Brown method presented 28.5%. In addition, according to the experimental results it can be concluded that it is very difficult to obtain a high level of accuracy concerning MOSFET switching losses, mainly due to the uncertainty when selecting datasheet information. Among the parameters that most influence the measurements, one could list the MOSFET transconductance, the channel threshold voltage and the parasitic inductances.