Solid-state Single Photon Avalanche Diodes (SPADs) have emerged as versatile photodetectors, playing a pivotal role in cutting-edge technologies such as photon counting, timing, and imaging. Their exceptional characteristics — high timing resolution, fast response, high gain, excellent quantum efficiency, and immunity to magnetic fields — make them a compelling alternative to traditional Photomultiplier Tubes (PMTs). SPADs’ unique ability to detect single photons, combined with their digital output and compact size, has positioned them as a superior choice for a wide range of applications in engineering, environmental monitoring, and healthcare. This review provides a comprehensive analysis of SPAD technology, focusing on their design principles, performance metrics, and applications. We begin by exploring the fundamental operating principles of SPADs and their key performance metrics. Next, we examine various SPAD structures across different technology nodes, offering a comparative analysis to highlight the latest advancements. Based on our review, we identify several techniques to enhance SPAD performance, including: doping profile engineering such as using high-voltage layers and doping compensation layers; upgrading optical stacks; and integration of high-speed front-end circuitry. We then introduce application-specific figures-of-merit and assess their relevance to the reviewed structures. Additionally, we address emerging trends in SPAD design, such as leveraging mask layer technology to achieve significant advancements. Finally, we conclude with an overview of research challenges, potential solutions, and future directions in SPAD technology, providing valuable insights to drive further innovations in this dynamic field.

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies.

Precise time measurement is a fundamental pillar of modern electronics, enabling applications that range from biomedical imaging and autonomous driving to quantum computing. Key to this capability is the Time-to-Digital Converter (TDC), a mixed-signal circuit that functions as an ultrafast stopwatch, resolving time intervals finer than a single logic gate delay. The integration of TDCs into standard CMOS technology, particularly alongside single-photon avalanche diodes, has been transformative. This synergy creates the “digital eyes” for Time-of-Flight (ToF) based 3D ranging, Light Detection and Ranging, and fluorescence lifetime imaging. Further, driven by industrial demands for higher performance and lower power, TDC architectures have evolved into highly efficient digital building blocks. To enable fair benchmarking across fifteen years of diverse design progress, this review introduces four application-aware figures of merit (FoMs). Our analysis, supported by a comprehensive evaluation of state-of-the-art implementations, reveals that no single architecture simultaneously optimizes all metrics. Instead, each architecture aligns with specific application needs: ring-oscillator (RO)-based TDCs offer the best overall balance of resolution, dynamic range, power, and area for practical, power-constrained systems. Stochastic and hybrid TDCs excel in resolution and sampling rate, albeit with reduced dynamic range, making them attractive for all-digital timing systems such as All-Digital Phase-Locked Loops. In contrast, counter-based (Nutt-method) TDCs provide wide dynamic range and high effective resolution, positioning them as key enablers for long-range ToF sensing. The paper concludes with a forward-looking discussion of emerging applications, persistent challenges, and future research directions in TDC development.

In this study, an ultra-low-voltage operational transconductance amplifier (OTA) operating from a 0.3 V supply, designed in a 45 nm CMOS process, is presented. To overcome the severe headroom constraints, the design employs a bulk-driven differential input stage combined with a current-reuse strategy, effectively enhancing transconductance while operating all transistors in the subthreshold region. This approach enables a rail-to-rail input common-mode range. A multipath Miller zero cancellation compensation technique ensures stability. The resulting OTA achieves an open-loop gain of 44.2 dB and a remarkable common-mode rejection ratio (CMRR) of 87.5 dB, all while consuming 23.3 nW of power. With a gain–bandwidth product of 9.9 kHz, a power supply rejection ratio (PSRR) of 41.1 dB, and an input noise of 1.0 μV/√Hz, this design is highly suitable for energy-constrained, low-frequency applications such as biomedical sensor interfaces and IoT nodes.