Electronic Design Automation (EDA) in analog Integrated Circuits (ICs) has been the focus of extensive research; however, unlike its digital counterpart, it has not achieved widespread adoption. In this systematic review, we discuss recent contributions in the last five years, highlighting methods that address data scarcity, topology exploration, process-voltage-temperature (PVT) variations, and layout parasitics. Our goal is to support researchers new to this domain by creating a comprehensive collection of references and practical application guidelines. We provide a methodological review of state-of-the-art machine learning (ML) approaches, including graph neural networks (GNNs), large language models (LLMs), and variational autoencoders (VAEs), which have been successfully applied to analog circuit sizing tasks. To the best of author’s knowledge, this is the first review to comprehensively explore the application of generative AI models in analog IC circuit design. We conclude that future research could focus on few-short learning with domain-adoption training of generative AI methods to simplify the design task such as human-tool interaction or guided design space exploration.

Solid-state Single Photon Avalanche Diodes (SPADs) have emerged as versatile photodetectors, playing a pivotal role in cutting-edge technologies such as photon counting, timing, and imaging. Their exceptional characteristics — high timing resolution, fast response, high gain, excellent quantum efficiency, and immunity to magnetic fields — make them a compelling alternative to traditional Photomultiplier Tubes (PMTs). SPADs’ unique ability to detect single photons, combined with their digital output and compact size, has positioned them as a superior choice for a wide range of applications in engineering, environmental monitoring, and healthcare. This review provides a comprehensive analysis of SPAD technology, focusing on their design principles, performance metrics, and applications. We begin by exploring the fundamental operating principles of SPADs and their key performance metrics. Next, we examine various SPAD structures across different technology nodes, offering a comparative analysis to highlight the latest advancements. Based on our review, we identify several techniques to enhance SPAD performance, including: doping profile engineering such as using high-voltage layers and doping compensation layers; upgrading optical stacks; and integration of high-speed front-end circuitry. We then introduce application-specific figures-of-merit and assess their relevance to the reviewed structures. Additionally, we address emerging trends in SPAD design, such as leveraging mask layer technology to achieve significant advancements. Finally, we conclude with an overview of research challenges, potential solutions, and future directions in SPAD technology, providing valuable insights to drive further innovations in this dynamic field.

In this article, all possible wideband fully differential second-order voltage-mode active all-pass filters (APFs) based on a common-source differential amplifier are systematically derived using two-port network modeling techniques and symbolic math CAD tools. The proposed APF structure is based on the generic two-transistor differential-pair and all possible combinations of the surrounding impedances. In particular, 26 transfer functions and a total of 180 APF circuits, all of which can have a pole quality factor (Q) value greater than unity, are found to be possible. Hence, the proposed topology can be used to produce APFs with dispersive delay as well as flat delay for true time delay elements. The operation of some APFs is verified with simulations and a selected circuit with tunable peak delay is designed and fabricated in a 65-nm CMOS process. The implemented filter achieved a maximum peak delay of 88.4 ps at 31 GHz, a constant delay of 11.5 ps over the frequency band 5-20 GHz, and a delay Q-factor (QD) value of 3.74, while consuming 1.74 mW from a 1-V supply voltage. The fabricated circuit occupies an area of 0.11x0.348 mm² and experimentally demonstrates an APF with the highest Q value of any published second-order APF known to the authors.

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies.

We propose a second-order RC-only voltage-mode active all-pass filter (APF) as an analog time-delay cell. The core circuit of the proposed APF is canonical and consists of only one transistor, one resistor, and two capacitors. Therefore, this design is area efficient, and it is suitable for low-GHz frequency applications, where conventional LC designs are not practical, due to large inductor sizes. The APF design equations are derived and the circuit noise and sources of non-ideality are discussed. The proposed 65nm CMOS APF is experimentally verified to demonstrate a wide-band range of 0.4-2GHz and a continuously tunable delay in the range of 30-57ps with an RMS delay variation error <1.42ps. The gain variation is below 0.75dB for all delay settings over the bandwidth. The circuit occupies only 1870μm2 while drawing 2.47mA from a 1V supply.