Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring single-cycle dead time and multi-channel expansion capabilities, with an original precision of 30 ps. Combined with jTDC’s dynamic caching mechanism using dual-page memory, this work employs a dual-cycle encoding and calibration. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. According to the experimental results, an optimal 3-tap heterogeneous TDL architecture achieves a resolution of 23.220 ps and a typical precision of 17.520 ps, whereas an optimal 4-tap heterogeneous TDL architecture demonstrates a resolution of 17.530 ps and a typical precision of 17.213 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.

To meet the application requirements of neutron detectors, a novel large-area microchannel plate photomultiplier tube with a gate function (G-MCP-PMT) was developed in this study. A kind of regular hexagonal mesh electrode as the gated electrode was designed to achieve excellent gating functions for target pulse signals. The photoelectron transmittances for different mesh electrode sizes and voltages were studied via numerical simulations. To increase the effective detection area of the photocathode, an electrostatic-focusing electrode was designed in the G-MCP-PMT. By optimizing the structure of the focusing electrode, an effective photocathode detection surface diameter of 80 mm was achieved based on commercially available MCPs with a diameter of 56 mm. By adjusting the channel diameter configurations of the dual MCPs, the output pulse peak and time response of the large-area G-MCP-PMT can be flexibly adjusted. The experimental results indicate that when the large-area G-MCP-PMT is operated at −2700 V, the gate establishment time is approximately 50 ns. The extinction ratio of the large-area G-MCP-PMT is higher than 3000:1, and the maximum linear output current is greater than 300 mA at 250 ns FWHM, meeting application needs in various fields such as white neutron detection and laser radar.

This study focuses on the optimization of discrete dynode electron multipliers (DEMs), which are critical for high-sensitivity signal detection in applications such as particle physics, nuclear reaction monitoring, and medical imaging. The research employs CST Studio Suite® electromagnetic simulations to analyze the impact of structural parameters — such as inter-dynode voltages, incidence angles, and surface coatings — on electron trajectory dynamics and multiplication efficiency. A 26-stage MgO dynode array is simulated, featuring dual output modes (analog and pulse counting) to accommodate varying ion input densities. The optimization process identifies key geometric parameters, including dynode spacing, curvature, and alignment, that significantly influence gain performance. The optimized design achieves a simulated gain of 1.8×10⁵ in analog mode and 5.5×10⁷ in pulse-counting mode, representing substantial improvements over baseline configurations. Experimental validation confirms the simulation trends, though discrepancies due to material degradation during assembly are noted. This work provides actionable insights for the design and optimization of high-performance DEMs, addressing challenges in achieving stable, high-gain operation over extended periods.