A 20-GHz low-power low-noise amplifier (LNA) in 65-nm CMOS is presented. The LNA is cascaded with a single-ended gₘ-boosted common-gate (CG) stage and a differential neutralized common-source (CS) stage. Current-reuse technique is employed to save the power consumption with little deterioration in gain and noise figure (NF). The transformer-based gₘ-boost technique in the CG stage and neutralization technique in CS stage further enhances the RF performances. Inter-stage magnetically coupled resonator (MCR) extends the bandwidth. An elaborate analysis of the current-reused CG-CS LNA using a transformer-based gₘ-boost technique and transformer-based MCR is proposed. Fabricated in 65-nm CMOS technology, the LNA achieves a measured power gain of 14.9 dB at 21 GHz with a -3-dB bandwidth of 4.8 GHz. The lowest NF is 3.3 dB at 19.5 GHz and is below 4 dB from 17 to 21 GHz. The LNA consumes 1.9 mW from a 1-V supply, with a chip area of 600 μm x 700 μm.

Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable broadband 5G and satellite communications. This paper details the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS and multi-layer hybrid PCB technologies. Both technologies attain high yield and low cost for mass production. Important beamforming building blocks are addressed and compared in detail. Demonstrators of integrated phased arrays are presented from circuit to board levels. The 1024- and 4096-element integrated phased arrays achieve the EIRP of 72.5 and 84.0 dBm respectively. Finally, relevant phased-array transceivers and antennas from the recent literature are discussed.

This article presents a four-element phased-array transceiver (TRX) front-end for millimeter-wave (mm-Wave) 5G new radio (NR). The effects of amplitude-to-phase (AM–PM) and amplitude-to-amplitude (AM–AM) distortions on error vector magnitude (EVM) are detailed. A three-stage highly linear wideband class-AB power amplifier (PA) is described, mitigating AM–PM and AM–AM distortions without degrading other performances. A matching network embedded transmitting/receiving (T/R) switch is proposed to support time division duplex (TDD). With the proposed technique, RF switch insertion losses are reduced in both transmitter (TX) and receiving (RX) modes. In each TRX element, phase and gain controls are achieved by a 6-bit vector-modulated phase shifter (VMPS) with a phase tuning range of 360° and a 6-bit attenuator with a gain tuning range of 31.5 dB, respectively. Fabricated in 65-nm bulk CMOS, the proposed packaged TRX demonstrates the measured peak gains of 25.5/14.2 dB with the gain ripples of less than 2.5/1.9 dB across 24–29.5 GHz in the TX/RX mode. The measured peak $P_{\text {1 dB}}$ is 17.6 dBm with a power added efficiency (PAE) of 20.4%. The measured minimum noise figure (NF) is 4.3 dB. The TRX achieves an output power of 7.9–8.9 dBm and an EVM of −25 dB with 8 $\times $ 100-MHz 5G NR frequency range 2 (FR2) orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signals across 24–29.5 GHz, covering 3rd generation partnership project (3GPP) 5G NR FR2 operating bands (i.e., n257, n258, and n261) around 26 GHz.

This paper presents an ultra-broadband 5-bit switched-type attenuator (STA). Three attenuation topologies are employed for the design of the attenuation cells, including the T-type, simplified T-type and Π -type topologies. For each attenuation topology, the optimal values of the series and shunt resistors are derived to achieve accurate amplitude tuning and ensure good impedance matching. The capacitive compensation technique is adopted by both the T-type and Π -type topologies to enhance the high-frequency performance. Based on the proposed optimization techniques, a systematic design methodology is developed for the STA. The 5-bit STA is implemented in 65-nm CMOS technology and occupies a core chip area of only 0.036 mm². It exhibits ultra-broadband operation with 15.5-dB amplitude tuning range and 0.5-dB tuning step. The insertion loss of the reference state is 1.5 - 5.9 dB from DC to 50 GHz. The return loss is better than 12 dB for all the 32 states. The RMS amplitude error and phase error are less than 0.25 dB and 3.5° over the DC - 50 GHz band.

In this article, a geometric method, along with the concept of the reference circle, is proposed for the analysis of reflective-type phase shifter (RTPS). Comprehensive analyses of popular reflective loads, including capacitive load (CL), resonated load (RL), and π -type load, are presented, revealing their limitations. The triple-resonating load technique is proposed to accomplish a full 360° phase shift range and suppress the loss variation. Further, a systematic design methodology for the RTPS using triple-resonating load is developed. Fabricated in 65-nm CMOS technology, the proposed RTPS occupies a core chip area of 0.076 μm². It achieves the first-ever 379° phase shift range at 29 GHz with only one control voltage. With dual-voltage control, a full 360° phase shift range with 8.3 ± 0.2 dB insertion loss is achieved. For both control methods, the return loss is better than 22.8 dB for all phase shift states.

This paper presents a passive vector-modulated phase shifter (VMPS). The passive X-type attenuator consisting of digitally controlled transistor-array units is employed to perform the phase-invertible gain tuning, and thus enables phase shift in all four quadrants. The Wilkinson-like power combiner is utilized to sum up the quadrature signals and avoid impedance mismatches. Analysis proves that the proposed passive VMPS can provide consistent phase-shift performance for bidirectional operation. The proof-of-concept VMPS is implemented in 40-nm CMOS technology and occupies a core chip area of 0.15 mm ² . Measured results prove that it can provide consistent bidirectional 6-bit phase-shift operation, with accurate phase tuning (i.e., RMS phase error <; 24°) and low gain error (i.e., ±0.6 dB) over the whole 70-90 GHz band.