Mohammad Kazem Anvarifard

Dr. Mohammad Kazem Anvarifard


Research Focus & Metrics

Academic Career Length

14Years (2013-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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6 December 2018 in Silicon
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MAMohammad Kazem Anvarifard
Mohammad Kazem Anvarifard
AOAli A. Orouji
Ali A. Orouji

2 March 2018 in IEEE Transactions on Electron Devices
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MAMohammad Kazem Anvarifard
Mohammad Kazem Anvarifard
AOAli Asghar Orouji
Ali Asghar Orouji
This brief is describing a useful idea to reform the distribution of the electric field for nanosilicon-on-insulator metal-oxide-semiconductors-field-effect transistors. The approach we benefit from it is to develop a part of the channel region into the drain region. This technique modulates the channel charge with the creation of an extra peak electric field in the developed channel/drain region interface. As a result, critical electric field of the new proposed structure at the end of the channel is successfully mitigated. DC and ac investigations revealed that the novel device has more reliability than a common device widely utilized in today's industry. The evaluation of both the common and proposed structures is handled by ATLAS simulator from SILVACO family. The important parameters in the cases of the short-channel effects, hot-carrier effects, switching speed, power gain, and parasitic capacitances are comprehensively studied to attain the best decision about the excellent electrical performance of the proposed device.

26 November 2019 in Silicon
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NBNazanin Baghban Bousari
Nazanin Baghban Bousari
MAMohammad Kazem Anvarifard
Mohammad Kazem Anvarifard
SHSaeed Haji-Nasiri
Saeed Haji-Nasiri

9 November 2020 in Journal of Materials Science: Materials in Electronics
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MAMohammad Kazem Anvarifard
Mohammad Kazem Anvarifard
ZRZeinab Ramezani
Zeinab Ramezani
IAIraj Sadegh Amiri
Iraj Sadegh Amiri
Khalil TamersitKhalil Tamersit
Khalil Tamersit
ANAlireza Mahdavi Nejad
Alireza Mahdavi Nejad

28 December 2018 in ECS Journal of Solid State Science and Technology
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MAMohammad Kazem Anvarifard
Mohammad Kazem Anvarifard
Double-Halo-Doping carbon nanotube field effect transistor (DH-CNTFET) has been recently suggested as a reliable and efficient device for the nanoscale applications which is a potential candidate to obsolete the conventional CNTFET (C-CNTFET), eventually. In this respect, the work aims to present an accurate compact analytical model for the drain current which is applicable in the different SPICE levels for circuit simulations. The paper captures the fundamental physic of a conventional CNTFET in order to develop a comprehensive and accurate analytical drain current model for the DH-CNTFET structure. Regarding the DH-CNTFET structure, important decision variables in the cases of ballistic carrier velocity, electron mobility, source/drain series resistance, threshold voltage, drain induced barrier lowering (DIBL) factor, fermi level to the band edge in the source region, subthreshold swing factor and band-to-band tunneling factor are introduced and globally searched by the PSO algorithm to achieve the most accurate relation for the drain current. The suggested compact analytical model is successfully compared with the realistic data extracted from the numerical simulation of the DH-CNTFET by full quantum mechanical Green's function approach. The results revealed that the compact analytical model predicts the drain current of the DH-CNTFET, accurately. As the other worthwhile effort, the work has proposed a compact analytical model for the gate-source and gate-drain capacitances providing it very attractive and suitable for the simulations under the circuit in the SPICE different levels.

20 October 2016 in IEEE Transactions on Device and Materials Reliability
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MAMohammad Kazem Anvarifard
Mohammad Kazem Anvarifard
Potential distribution of a silicon-on-insulator metal-semiconductor field effect transistor (SOI-MESFET) is successfully controlled by introducing a new structure. The structure we established, utilizes a P-type layer embedded in the drift region. Also, the doping engineering is applied to the proposed structure in order to more enhance the performance superiority of the novel structure called SPL-DE SOI MESFET. The P-type layer and doping engineering control the potential distribution and help the proposed structure to improve the important parameters, such as breakdown voltage, driving current, power gains, oscillation frequency, transconductance, maximum output power density, and gate–drain parasitic capacitance. As a result, the SPL-DE SOI MESFET has superior electrical performances in comparison with the similar device based on the conventional structure thus taking into account the special considerations for the high-voltage and high-frequency applications.