Khalil Tamersit

Dr. Khalil Tamersit

University of Guelma, Guelma, Algeria
orcid

Research Focus & Metrics

Academic Career Length

14Years (2013-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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5 April 2016 in IEEE Sensors Journal
Verified
Journal Article
Closed access
Khalil TamersitKhalil Tamersit
Khalil Tamersit
FDFaycal Djeffal
Faycal Djeffal
In this paper, new sensors based on a double-gate (DG) graphene nanoribbon field-effect transistor (GNRFET), for high-performance DNA and gas detection, are proposed through a simulation-based study. The proposed sensors are simulated by solving the Schrödinger equation using the mode space non-equilibrium Green's function formalism coupled self-consistently with a 2D Poisson equation under the ballistic limits. The dielectric and work function modulation techniques are used for the electrical detection of DNA and gas molecules, respectively. The behaviors of both the sensors have been investigated, and the impacts of variation in geometrical and electrical parameters on the sensitivity of sensors have also been studied. In comparison to other FET-based sensors, the proposed sensors provide not only higher sensitivity but also better electrical and scaling performances. The obtained results make the proposed DG-GNRFET-based sensors as promising candidates for ultra-sensitive, small-size, low-power and reliable CMOS-based DNA, and gas sensors.

24 December 2020 in IEEE Transactions on Circuits and Systems II: Express Briefs
Verified
Journal Article
Closed access
MJMohammad Khaleqi Qaleh Jooq
Mohammad Khaleqi Qaleh Jooq
MMMohammad Hossein Moaiyeri
Mohammad Hossein Moaiyeri
Khalil TamersitKhalil Tamersit
Khalil Tamersit
Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates will diminish these advantages in practice. In this paper, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units.

22 September 2021 in IEEE Transactions on Circuits and Systems I: Regular Papers
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Journal Article
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FBFereshteh Behbahani
Fereshteh Behbahani
MJMohammad Khaleqi Qaleh Jooq
Mohammad Khaleqi Qaleh Jooq
MMMohammad Hossein Moaiyeri
Mohammad Hossein Moaiyeri
Khalil TamersitKhalil Tamersit
Khalil Tamersit
Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four 1x 3 kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt's figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts.

27 June 2019 in IEEE Sensors Journal
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Journal Article
Closed access
Khalil TamersitKhalil Tamersit
Khalil Tamersit
FDF. Djeffal
F. Djeffal
In this paper, we assess the performance of a new label-free DNA nanosensor based on ballistic carbon nanotube field-effect transistor (CNTFET). The proposed label-free biosensor employs the mechanism of an ultrascaled CNTFET in conjunction with the dielectric and charge modulation concept to electronically detect the neutralized and charged DNA molecules. The proposed DNA nanosensor is endowed with a sensitive channel based on a zigzag carbon nanotube (Z-CNT). The investigation is based on a rigorous quantum simulation, which solves self-consistently the Schrödinger and Poisson equations within the non-equilibrium Green’s function (NEGF) formalism framework. The threshold voltage shift is considered as a biosensing metric. The simulation study includes the potential distribution, Z-CNT charge density, lateral electric-field, IDS-VGS transfer characteristics, subthreshold swing, current spectrum, and sensitivity. Moreover, a parametric analysis is performed to study the impact of ultrascaling issue on the sensitivity behavior. The obtained results empower the proposed nanobiosensor to be considered as a promising candidate for high-performance labelfree DNA sensing applications at the nanoscale domain, where the dimensions of bio-measurands are comparable to those of nanobiosensors.

28 September 2022 in IEEE Transactions on Electron Devices
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Journal Article
Closed access
MJMohammad Khaleqi Qaleh Jooq
Mohammad Khaleqi Qaleh Jooq
MMMohammad Hossein Moaiyeri
Mohammad Hossein Moaiyeri
Khalil TamersitKhalil Tamersit
Khalil Tamersit
Preserving the data stored in a static random access memory (SRAM) during power gating or a sudden power outage is a necessary but costly need. This work proposes an ultraefficient auto-nonvolatile ternary SRAM (ATSRAM) cell using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs). By harnessing the unique features in Fe-CNTFETs, the proposed ATSRAM utilizes only 12 transistors. The proposed design can automatically perform backup and restore operations without additional resources and nonvolatile elements during a power outage. This unique specification eliminates the redundancies usually required to provide nonvolatility. The utilized hysteretic cross-coupled two-transistor standard ternary inverters (STIs) provide a superior static noise margin (SNM) beyond the binary SRAMs and the ideal noise margin limitation ( $\textit{V}_{\text{DD}}$ /4). The proposed ATSRAM array structure benefits from a row-shared supply disconnector to mitigate the static current drawn from the power supply during data retention. Our results demonstrate that the proposed ATSRAM indicates, on average, 40% improvement in transistor count, 2.8 times higher SNMs, 27% reduction in total power consumption, and 41% (66%) improvement in the read (write) energy compared with the state-of-the-art volatile ternary SRAMs. In a $\text{32}$ $\times $ $\text{32}$ ternary array configuration, 94% (98%) improvement in the read (write) energy is obtained compared with the other counterparts. Our design methodology provides a new paradigm for designing ultraefficient and ultracompact nonvolatile multivalued logic (MVL) memories using ferroelectric-based FETs.

1 September 2018 in Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
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Journal Article
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Khalil TamersitKhalil Tamersit
Khalil Tamersit
FDFayçal Djeffal
Fayçal Djeffal