This paper presents a comprehensive register transfer-level (RTL) fault injection study targeting the program counter (PC) of the LEON3 processor, a SPARC V8-compliant core widely used in safety-critical and radiation-prone embedded applications. Using the enhanced NETFI+ framework, over four million faults, including single-event upsets (SEUs), multiple-bit upsets (MBUs), and single-event transients (SETs), were systematically injected into the PC across all pipeline stages. The analysis reveals that early stages, particularly Fetch (FE), Decode (DE), Register Access (RA), and Execute (EX), are highly sensitive to SEU and MBU faults. The propagation of errors detected in the two early stages of the pipeline (FE and DE) is classified with an important percentage of halt execution and timeout traps. Intermediate stages, such as RA and EX, exhibited a higher incidence of silent data corruption and halt execution, while the Memory (ME) and Exception (XC) stages demonstrated greater resilience through fault masking. SET faults were mostly transient and masked, though they occasionally resulted in control flow anomalies. In addition to error classification, detailed trap and exception analysis was performed to characterize fault-induced failure mechanisms. The findings underscore the need for pipeline-stage-specific hardening strategies and highlight the value of simulation-based fault injection for early design validation in safety-critical embedded processors.

The reliability of embedded processors in safety- and mission-critical domains is increasingly threatened by radiation-induced soft errors, particularly multiple-cell upsets (MCUs) that simultaneously corrupt adjacent cells in external SDRAM. While prior studies on the LEON3 processor have largely focused on single-event upsets (SEUs) in internal SRAM structures, they overlook MCU effects in off-chip SDRAM, a critical gap that limits fault coverage and compromises system-level reliability assessment in modern high-density embedded systems. This paper presents an SDRAM-based fault injection framework using FPGA emulation to evaluate the impact of MCUs on the LEON3 soft-core processor, with faults directly injected into the external memory subsystem where data corruptions can rapidly propagate into system-level failures. The methodology injects spatially correlated two-bit MCUs directly into SDRAM during realistic workload execution. Three architecturally diverse benchmarks were analyzed, each representing a distinct computational workload: a numerical (matrix multiplication), signal-processing (FFT), and a cryptographic (AES-128 encryption) application, chosen to capture arithmetic-intensive, iterative, and control-intensive execution profiles, respectively. The results reveal a distinct workload-dependent vulnerability profile. Matrix multiplication exhibited >99.99% fault activation, with outcomes overwhelmingly dominated by data store errors. FFT showed >97% activation in steady-state execution, following an initial phase sensitive to alignment and data access exceptions. AES displayed 88.12% non-propagating faults, primarily due to injections in inactive memory regions, but remained exposed to critical memory access violations and control-flow exceptions that enable fault-based cryptanalysis. These findings demonstrate that SEU-only models severely underestimate real-world MCU risks and underscore the necessity of selective, workload-aware fault-tolerance strategies: lightweight ECC for cryptographic data structures, alignment monitoring for signal processing, and algorithm-based fault tolerance (ABFT) for numerical kernels. This work provides actionable insights for hardening LEON3-based systems against emerging multi-bit threats in radiation-rich and adversarial environments.

Multi-bit upsets (MBUs) are a growing reliability threat in high-density SDRAM, particularly in radiation-prone embedded systems. This paper presents a large-scale FPGA-based fault injection (FI) study targeting external SDRAM in a cache-enabled LEON3 SPARC V8 processor, with over 300,000 dual-bit MBUs injected across three diverse workloads: Fast Fourier transform (FFT), matrix multiplication (MulMatrix), and advanced encryption standard (AES). Our results reveal a profound dependence of MBU manifestation on application semantics: memory-intensive benchmarks (FFT, MulMatrix) exhibit high fault detectability through data store and access exceptions, while the AES workload demonstrates exceptional intrinsic masking, with the vast majority of MBUs producing no observable effect. These results demonstrate that processor vulnerability to MBUs is not uniform but fundamentally shaped by workload characteristics, including memory access patterns, control flow regularity, and algorithmic redundancy. The study provides a hardware-validated foundation for designing workload-aware fault tolerance strategies in space-grade and safety-critical embedded platforms.

This paper presents a register-transfer-level (RTL) fault injection study of the LEON3 processor’s internal memory subsystem under single-event upsets (SEUs). The analysis targets four key components: the instruction cache (I-cache), data cache (D-cache), AHB bus control interface, and memory controller (MCTRL), all of which are unprotected in the standard LEON3 configuration. Using the NETFI+ fault injection framework, multi-cycle SEUs are injected into sequential elements across these blocks while executing a memory-intensive benchmark. The results show that the AHB interface is extremely fragile, with every fault causing execution failure. The memory controller, though architecturally invisible, frequently induces precise SPARC V8 traps such as window overflow and illegal instruction through indirect data-path corruption. The data cache is identified as the primary source of silent data corruption (SDC), while the instruction cache exhibits partial natural masking but remains susceptible to control-flow errors. These findings highlight the disproportionate impact of unprotected protocol and controller logic on system reliability and inform targeted hardening strategies for LEON3-based embedded systems in radiation-prone environments.

Introduction/Objective: This work presents a fully integrated Integer-N frequency synthesizer targeting multi-standard short-range wireless protocols operating in the 2.4 GHz ISM band, including Bluetooth LE (BLE 5.4), ZigBee, Thread, and Wi-Fi coexistence. The design addresses the need for fast lock time, low residual FM, excellent spectral purity, and low-cost implementation in resource-constrained IoT applications. Methods: The synthesizer is implemented in 0.35 µm CMOS and centers on a resistorless discretetime loop filter (DT-LPF), the core innovation of this work, which eliminates on-chip resistors entirely by replacing them with a delayed charge injection mechanism using switched-capacitor networks. This approach improves stability of the loop, eliminates thermal noise associated with passive resistors, and by avoiding on-chip resistors entirely, reduces sensitivity to resistor mismatch and process variation, while enabling a more compact loop filter topology in standard CMOS processes. Complementing this, the design employs a gm/Id-optimized differential LC-VCO, a dead-zone-free tri-state PFD with 1 ns reset-path delay, and a current-scaled CML multi-modulus 2/3 divider that reduces highfrequency power dissipation. All blocks are co-optimized for 1 MHz reference frequency operation, and the system is fully designed and simulated using industry-standard EDA tools. Results: The PLL achieves a 230 MHz tuning range (2.28–2.51 GHz) with 1 MHz channel resolution, fully covering the 79-channel Bluetooth band, ZigBee/Thread channels (2.405–2.480 GHz), and the entire 2.4 GHz ISM band used by Wi-Fi. It locks in approximately 100 µs, satisfying the 30%. Despite using a lowcost 0.35 µm process, the architecture rivals advanced-node PLLs in FoM and protocol compliance. The 1 MHz reference frequency and explicit residual FM validation ensure real-world suitability for Bluetooth and ZigBee, metrics often omitted in recent works. The design demonstrates that architectural innovation can compensate for technological constraints in cost-sensitive IoT. Conclusion: The proposed synthesizer meets all essential performance metrics for ISM-band wireless protocols and demonstrates architectural efficiency and scalability. Its design offers a competitive and low-cost solution for power-sensitive short-range communication systems, particularly in cost-constrained IoT applications where advanced CMOS nodes are economically prohibitive.

This work presents an experimental analysis of single-event upset (SEU) vulnerability in the program counter (PC) of the LEON3 soft-core processor and evaluates triple modular redundancy (TMR) as a hardware-level mitigation strategy. Using Field programmable gate arrays (FPGA)-based emulation with the NETFI+ fault injection framework, SEUs are injected into the 30 most significant bits of the PC across all active pipeline stages. Results reveal that vulnerability is highly stage-dependent: the fetch and decode stages exhibit 100% sensitivity, as any bit-flip immediately disrupts control flow, while later stages (RA, EX, ME) are fully masked due to natural overwriting of PC values. The Exception stage shows only marginal sensitivity (0.02%). To address this localized fragility, TMR is applied to the entire integer unit, triplicating pipeline logic. Under single-replica SEU injection, TMR achieves 0% sensitivity, fully masking all faults. Even in pessimistic multi-replica fault scenarios, where two or all three replicas are simultaneously corrupted, the system demonstrates strong resilience, reducing observable error sensitivity by up to 10× compared to the unprotected baseline. Resource overhead includes a 56% increase in Look-up-tables and 28% in registers on a Xilinx Virtex-5 FPGA. These results confirm that the PC is the dominant source of SEU-induced control-flow failure in LEON3 and that TMR provides complete protection in realistic single-fault conditions while maintaining robustness under rare multi-fault events. The study establishes TMR as a highly effective countermeasure for LEON3-based systems operating in radiation-prone aerospace and space environments.