Agriculture in arid and semi-arid regions faces critical challenges of water scarcity, irregular rainfall, and the high cost of monitoring systems. Most existing Internet of Things (IoT) platforms for precision agriculture are expensive, energy-intensive, and rely on cellular or grid connectivity, which limits their adoption by smallholder farmers. To overcome these issues, this work presents a hybrid Espressif peer-to-peer protocol (ESP-NOW) / long range (LoRa) IoT monitoring system. The architecture combines ESP8266 sensor nodes, an ESP32 primary aggregator, and a Raspberry Pi 4 gateway, integrating ESP-NOW for local ultra-low-power communication and LoRa for long-range data transmission. In operation, the ESP8266 nodes periodically acquire environmental data and send it via ESP-NOW to the ESP32 primary, which aggregates the packets and forwards them through LoRa to the Raspberry Pi gateway for storage, visualization, and analysis. All sensor data are stored in a MySQL database and visualized in real time through a web dashboard. The sensing modules were calibrated under laboratory conditions using reference instruments to ensure accuracy, achieving correlation coefficients ( $R^{2}$ ) between 0.95 and 0.97. Field deployment in a Tunisian wheat plot further confirmed stable performance, with less than 3% nighttime battery discharge and a packet delivery ratio above 95% up to 2 km. Costing under 600 EUR, the proposed system provides a validated, scalable, and affordable IoT solution for precision agriculture in resource-constrained environments.

This paper presents a comprehensive register transfer-level (RTL) fault injection study targeting the program counter (PC) of the LEON3 processor, a SPARC V8-compliant core widely used in safety-critical and radiation-prone embedded applications. Using the enhanced NETFI+ framework, over four million faults, including single-event upsets (SEUs), multiple-bit upsets (MBUs), and single-event transients (SETs), were systematically injected into the PC across all pipeline stages. The analysis reveals that early stages, particularly Fetch (FE), Decode (DE), Register Access (RA), and Execute (EX), are highly sensitive to SEU and MBU faults. The propagation of errors detected in the two early stages of the pipeline (FE and DE) is classified with an important percentage of halt execution and timeout traps. Intermediate stages, such as RA and EX, exhibited a higher incidence of silent data corruption and halt execution, while the Memory (ME) and Exception (XC) stages demonstrated greater resilience through fault masking. SET faults were mostly transient and masked, though they occasionally resulted in control flow anomalies. In addition to error classification, detailed trap and exception analysis was performed to characterize fault-induced failure mechanisms. The findings underscore the need for pipeline-stage-specific hardening strategies and highlight the value of simulation-based fault injection for early design validation in safety-critical embedded processors.

Non-invasive glucose monitoring remains a significant challenge in diabetes management, with existing approaches often limited by poor accuracy, high cost, or patient discomfort. Microwave-based biosensors offer a promising label-free alternative by exploiting the dielectric contrast between glucose and water. This paper presents a compact, dual-band concentric square-shaped split-ring resonator (SRR-type) biosensor fabricated on a low-cost FR-4 substrate for aqueous glucose detection. The sensor leverages electric field confinement in inter-ring gaps to transduce glucose-induced permittivity changes into measurable shifts in resonance frequency and reflection coefficient. Experimental results demonstrate a linear, monotonic response across the clinical range up to 250 mg/dL, with a frequency-domain sensitivity of 1.964 MHz/(mg/dL) and amplitude-domain sensitivity of 0.0332 dB/(mg/dL), achieving high coefficients of determination (R² = 0.9956 and 0.9927, respectively). The design achieves a normalized size of 0.137 λ_g², combining high sensitivity and compact size within a scalable platform. Operating in the UWB-adjacent band (2.76–3.25 GHz), the proposed biosensor provides a practical, reproducible, and PCB-compatible solution for next-generation label-free glucose monitoring.

The reliability of embedded processors in safety- and mission-critical domains is increasingly threatened by radiation-induced soft errors, particularly multiple-cell upsets (MCUs) that simultaneously corrupt adjacent cells in external SDRAM. While prior studies on the LEON3 processor have largely focused on single-event upsets (SEUs) in internal SRAM structures, they overlook MCU effects in off-chip SDRAM, a critical gap that limits fault coverage and compromises system-level reliability assessment in modern high-density embedded systems. This paper presents an SDRAM-based fault injection framework using FPGA emulation to evaluate the impact of MCUs on the LEON3 soft-core processor, with faults directly injected into the external memory subsystem where data corruptions can rapidly propagate into system-level failures. The methodology injects spatially correlated two-bit MCUs directly into SDRAM during realistic workload execution. Three architecturally diverse benchmarks were analyzed, each representing a distinct computational workload: a numerical (matrix multiplication), signal-processing (FFT), and a cryptographic (AES-128 encryption) application, chosen to capture arithmetic-intensive, iterative, and control-intensive execution profiles, respectively. The results reveal a distinct workload-dependent vulnerability profile. Matrix multiplication exhibited >99.99% fault activation, with outcomes overwhelmingly dominated by data store errors. FFT showed >97% activation in steady-state execution, following an initial phase sensitive to alignment and data access exceptions. AES displayed 88.12% non-propagating faults, primarily due to injections in inactive memory regions, but remained exposed to critical memory access violations and control-flow exceptions that enable fault-based cryptanalysis. These findings demonstrate that SEU-only models severely underestimate real-world MCU risks and underscore the necessity of selective, workload-aware fault-tolerance strategies: lightweight ECC for cryptographic data structures, alignment monitoring for signal processing, and algorithm-based fault tolerance (ABFT) for numerical kernels. This work provides actionable insights for hardening LEON3-based systems against emerging multi-bit threats in radiation-rich and adversarial environments.

Multi-bit upsets (MBUs) are a growing reliability threat in high-density SDRAM, particularly in radiation-prone embedded systems. This paper presents a large-scale FPGA-based fault injection (FI) study targeting external SDRAM in a cache-enabled LEON3 SPARC V8 processor, with over 300,000 dual-bit MBUs injected across three diverse workloads: Fast Fourier transform (FFT), matrix multiplication (MulMatrix), and advanced encryption standard (AES). Our results reveal a profound dependence of MBU manifestation on application semantics: memory-intensive benchmarks (FFT, MulMatrix) exhibit high fault detectability through data store and access exceptions, while the AES workload demonstrates exceptional intrinsic masking, with the vast majority of MBUs producing no observable effect. These results demonstrate that processor vulnerability to MBUs is not uniform but fundamentally shaped by workload characteristics, including memory access patterns, control flow regularity, and algorithmic redundancy. The study provides a hardware-validated foundation for designing workload-aware fault tolerance strategies in space-grade and safety-critical embedded platforms.