Fire monitoring systems have usually been based on a single sensor such as smoke or flame. These single sensor systems have been unable to distinguish between true and false presence of fire, such as a smoke from a cigarette which might cause the fire alarm to go off. Consuming energy all day long and being dependent on one sensor that might end with false alert is not efficient and environmentally friendly. We need a system that is efficient not only in sensing fire accurately, but we also need a solution which is smart. In order to improve upon the results of existing single sensor systems, our system uses a combination of three sensors to increase the efficiency. The result from the sensor is then analyzed by a specified rule-set using an AI-based fuzzy logic algorithm; defined in the purposed research, our system detects the presence of fire. Our system is designed to make smart decisions based on the situation; it provides feature updated alerts and hardware controls such as enabling a mechanism to start ventilation if the fire is causing suffocation, and also providing water support to minimize the damage. The purposed system keeps updating the management about the current severity of the environment by continually sensing any change in the environment during fire. The purposed system proved to provide accurate results in the entire 15 test performed around different intensities of a fire situation. The simulation work for the SMDD is done using MATLAB and the result of the experiments is satisfactory.

The exponential function $a^x$ is widespread in many fields of science. Its calculation is a complicated issue for Central Processing Units (CPUs) and Graphics Processing Units (GPUs), as well as for specialised Digital Signal Processing (DSP) processors, such as Intelligent Processor Units (IPUs), for the needs of neural networks. This article presents some simple and accurate exponential function calculation algorithms in half, single, and double precision that can be prototyped in Field-Programmable Gate Arrays (FPGAs). It should be noted that, for the approximation, the use of effective polynomials of the first degree was proposed in most cases. The characteristic feature of such algorithms is that they only contain fast ‘bithack’ operations (‘bit manipulation technique’) and Floating-Point (FP) addition, multiplication, and (if necessary) Fused Multiply-Add (FMA) operations. We published an article on algorithms for this class of function recently, but the focus was on the use of approximations of second-degree polynomials and higher, requiring two multiplications and two additions or more, which poses some complications in FPGA implementation. This article considers algorithms based on piecewise linear approximation, with one multiplication and one addition. Such algorithms of low complexity provide decent accuracy and speed, sufficient for practical applications such as accelerators for neural networks, power electronics, machine learning, computer vision, and intelligent robotic systems. These are FP-oriented algorithms; therefore, we briefly describe the characteristic parameters of such numbers.

The square root is one of the most used functions in many different engineering and scientific applications. We propose new methods for calculating the square root function that are based on the Newton–Raphson method with Heron iteration. A modification of Heron’s formula combined with an improved selection of the magic constants enables a significant reduction of the maximum relative error (MRE). Simple modifications to the Newton–Raphson formula and the magic number method enable implementation on platforms with limited hardware resources, such as microcontrollers and FPGAs, with variable accuracy. Implementations of new approximation algorithms in the C programming language were carefully tested and evaluated against their software and hardware counterparts on the most popular platforms, e.g., CPUs from Intel, AMD and ARM, GPU from Nvidia and IPU from Graphcore. The proposed numerical algorithms are shown to be superior in terms of computational time, the number of clock cycles, accuracy, MRE, and root mean square deviation.

The coordinate rotation digital computer (CORDIC) algorithm is a popular method used in many fields of science and technology. Unfortunately, it is a time-consuming process for central processing units (CPUs) and graphics processing units (GPUs), and even for specialized digital signal processing (DSP) solutions. The CORDIC algorithm is an alternative for Newton-Raphson numerical calculation and for the FPGA based resource-expensive look-up-table (LUT) method. Various modifications of the CORDIC algorithm allow to speed up the operation of hardware in edge computing devices. With that context taken into consideration, this article presents a fast and accurate square root floating point (SQRT FP) CORDIC function which can be implemented in field programmable gate arrays (FPGAs). The proposed algorithm offers low-complexity, decent accuracy and speed, and is sufficient for digital signal processing (DSP) applications, such as digital filters, accelerators for neural networks, machine learning and computer vision applications, and intelligent robotic systems.

FPGAs are well suited for prototyping complex digital systems for industrial and research purposes, as well as for the practical application of artificial intelligence (AI) methods in industrial autonomous control, automotives and space. FPGAs serve as platforms for inferring based on AI algorithms. In recent years, an increase in FPGA system applications with respect to advanced computing functions for physical and chemical research in space has been observed. Research on the reliability of applications operating in the above-mentioned areas exposed to radiation is of particular importance. Testing applications implemented on FPGAs requires the development of new methods that differ significantly from those intended for Application-Specific Integrated Circuits (ASICs). The FPGA logic is realized by SRAM-Based Look-Up Tables (LUTs). SRAM is relatively susceptible to single-event upsets (SEUs) generated by cosmic radiation. The existing fault injection (FI) tools do not model the faults generated by SEUs in SRAM-based FPGAs precisely enough. New FI tools are crucial for evaluating newly developed FPGA-specific tests. Thus, we developed a new tool that uses an accurate SEU model in LUTs. This new tool is written in Perl, and its tasks are to inject faults into the structural VHDL description and to control the CADENCE simulator. The novelty of this solution is that the tool models SEUs by modifying the logical functions generated by the LUTs. Furthermore, in this way, stuck-at faults at the LUT inputs and outputs can also be modeled. This method involves modifying the “INIT” parameters in the structural VHDL. Our tool was evaluated using several test programs, and a high fault coverage (FC) of 94.76% was achieved. This tool can be used to examine any LUT-based FPGA technology regardless of its implementation age. Moreover, during our research, a new mechanism of generating so-called logical redundancies caused by the injection of single faults in LUTs was discovered. This is a side effect of FI in LUTs, which makes it impossible to achieve 100% fault coverage of applications implemented on FPGAs. The mechanism of this phenomenon does not occur when injecting traditional stuck-at faults.

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.