Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures.

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (LG) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current (ION) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (IOFF), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

In this paper, we study the impact of random discrete dopants in the source/drain (S/D) leads on the current variability of a gate-all-around Si nanowire transistor. Due to the strong inhomogeneities of the self-consistent electrostatic potential, a fully 3D real-space nonequilibrium Green's function (NEGF) formalism is used. N-channel transistors with random discrete donors in the S/D regions varying in both numbers and locations have been simulated. We have studied the impact of quasi-bound (QB) states and transmission resonances associated with the attractive potential of the donors on the screening of the impurities and on the current transport. The convergence of the coupled 3D Poisson-NEGF equations for narrow wires with discrete dopants is cumbersome due to the quasi-discrete nature of QB states and resonances of the attractive impurity potential. We present a robust solution strategy dealing with the convergence challenges. Large variations in the on-current and modest variations in the subthreshold slope are observed in the I _D-V _G characteristics when comparing devices with microscopically different discrete dopant configurations. We have also estimated the access resistance associated with the random dopant regions in the source and the drain leads and find very good agreement with the resistance estimated from the bulk silicon mobility at the same doping concentration.

In this paper, we review and extend recent work on the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors. The electron transport is described using the nonequilibrium Green's function formalism. Full 3-D real-space and coupled-mode-space repre sentations are used. Two different cross sections (i.e., 2.2 × 2.2 and 4.2 × 4.2 nm²) and two different channel lengths (i.e., 6 and 12 nm) have been considered. The resistivity associated with discrete dopants can be estimated from the averaged current-voltage characteristics. The threshold-voltage variability and the sub threshold-slope variability are reduced greatly in the transistors with longer channel length. Both are smaller at equivalent channel lengths in the 2.2 × 2.2 nm² device due to better electrostatic integrity. At the same time, the ON-state-current variability associated with the varying resistance of the access regions is virtually independent of the channel length. However, it is reduced greatly in the 4.2 × 4.2 nm² transistor due to a fourfold increase in the number of dopants in the access regions and corresponding self-averaging effects. Finally, we present results for the smallest transistor combining two sources of variability (i.e., discrete random dopants and surface roughness) and phonon scattering.

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with $\sigma ~{V}_{T}$ values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ( $\sigma {V}_{T}$ = 8 mV) and minimally influenced by the GER ( $\sigma {V}_{T} \approx 4$ mV). The variability of NS FETs makes them strong candidates to replace FinFETs.

An efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Green's functions approach. Finally, the simulated I_D-V_G characteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data.