This paper presents polychronous oscillatory cellular neural networks, designed for solving graph coloring problems. We propose to apply the Potts model to the four-coloring problem, using a network of locally connected oscillators under superharmonic injection locking. Based on our mapping of the Potts model to injection-locked oscillators, we utilize oscillators under divide-by-4 injection locking. Four possible states per oscillator are encoded in a polychronous fashion, where the steady state oscillator phases are analogous to the time-locked neuronal firing patterns of polychronous neurons. We apply impulse sensitivity function (ISF) theory to model and optimize the high-order injection locking of the oscillators. CMOS circuit design of a polychronous oscillatory neural network is presented, and coloring of a geographic map is demonstrated, with simulation results and design guidelines. There is good agreement between theory and Spectre simulation.

Subthreshold analog circuits are attractive for low-power, large-scale neuromorphic systems. However, subthreshold currents are exponentially sensitive to temperature and device mismatch, and a compact model that accounts for these effects is needed. We develop an analytical compact model with mismatch and temperature variation for subthreshold MOS devices. The model only requires an initial set of Monte Carlo (MC) simulations on individual devices for parameter extraction. Then the designer can use its parameterized analytical expressions for circuit design, instead of running repeated MC simulations on large circuits. We apply this model to a subthreshold current mirror design example. Good agreement between the developed model and Spectre simulations is achieved in a 28-nm fully-depleted silicon-on-insulator (FDSOI) process. The model is general and can also guide the design of other subthreshold circuits, such as low-power silicon neurons. It has been used to design Braindrop, the first neuromorphic chip programmed at a high level of abstraction.

Analysis and design of a tetrahedral oscillator is presented. Expressions for the startup condition and oscillation frequency are derived. A phase noise analysis of thermal and flicker noise is carried out, using the impulse sensitivity function theory. The noise contribution of each type of transistor is studied, and the dominant and negligible cyclostationary noise sources are identified. There is good agreement among the theory and Spectre simulation. Design guidelines based on the analysis are provided.

This paper presents quantum computing gate emulation using polychronous oscillatory cellular neural networks. The oscillatory neural network consists of locally interacting ring oscillators and control switches, in a standard CMOS process. We apply impulse sensitivity function (ISF) theory to model the injection locking of the oscillators. We show the design of universal quantum gate emulation with oscillator circuits. Quantum circuits for the Greenberger–Horne–Zeilinger State and W State are emulated using CMOS oscillators and switches. Spectre simulation results agree with the quantum circuit theory.

This brief presents an approach to solve Max 3-Cut problems using tripolar oscillatory cellular neural networks. We demonstrate the solution to Max 3-Cut can be formulated in terms of minimizing the Potts Hamiltonian. We propose to minimize the Potts Hamiltonian using a network of connected oscillators under divide-by-3 injection locking. We derive the steady state solution of the oscillator network by applying impulse sensitivity function (ISF) theory. We design a CMOS tripolar oscillator network circuit for computing the Max 3-Cut of a triforce graph (first-order Sierpiński triangle graph). We develop a second circuit to perform image segmentation, using signed (positive/negative) couplings. We then extend our circuit to simulate the dynamics of social network alliances, using a combination of signed and weighted couplings that play an essential role in computing Max 3-Cut. Spectre simulation results are in good agreement with the theoretical analysis.

This letter describes a differential edge modulation signaling scheme for a wireline link where the edge position is differentially modulated on a pair of wires such that data bits are recovered when these signals sample each other. Therefore, this clock-encoded modulation scheme eliminates the need for receiver side clock generation and timing recovery and enables matched source-synchronous jitter tracking with >500-MHz bandwidth. An agile multiplying injection-locked oscillator drives the link and dynamically scales the data rate from 3 to 10 Gb/s with less than 10-ns response time. Using a decision-based time-domain equalizer, the link can compensate the 20-dB loss at 10-Gb/s consuming only 19.4 mW, and scales to 10 mW at 3 Gb/s without supply scaling.