Random number generators play a critical role in ensuring information security, supporting encrypted communications, and preventing data leakage. However, the random number generators widely used in hardware are faced with potential threats such as environmental disturbances and fault injection attacks. Especially in automotive-grade environments, chips encounter threat scenarios involving multidimensional fault injection, which may lead to functional failures or malicious exploitation, endangering the security of the entire system. This paper focuses on a Counter Mode Deterministic Random Bit Generator (CTR-DRBG) based on the AES-128 algorithm and implements a hardware prototype system compliant with the NIST SP 800-22 standard on an FPGA platform. Centering on typical fault modes such as temperature disturbances, voltage glitches, electromagnetic interference, and bit flips, single-dimensional and multidimensional fault injection and simulated fault injection experiments were designed and conducted. The impact characteristics and sensitivities of electromagnetic faults, voltage faults, and temperature faults regarding the output sequences of random numbers were systematically evaluated. The experimental results show that this type of random number generator exhibits modular-level differential vulnerability under physical disturbances, especially in the data transmission processes of encryption paths and critical registers, which demonstrate higher sensitivity to flip-type faults. This research provides a feasible analysis framework and practical basis for the security assessment and fault-tolerant design of random number generators, possessing certain engineering applicability and theoretical reference value.

The output quality of random-number sources directly affects the security of cryptographic systems. Physical-noise degradation, environmental disturbance, device aging, and fault injection may increase output bias, correlation, and predictability. This paper presents a resource-conscious on-chip entropy-quality supervisor for random-number source output streams. The design uses non-overlapping 1024-bit measurement windows and a shared feature engine for bit counts, directional transition counts, and run information. These features support repetition-count, adaptive-proportion, and low-toggle checks, together with two-bit pattern-concentration and first-order conditional-transition indicators, exponentially weighted moving-average trend monitoring, comprehensive scoring, and a seven-bit alarm bitmap. The RTL accepts a 32-bit valid-data interface, makes one decision every 32 valid words, and is integrated into an Artix-7 XC7A35T project configured with a 50 MHz system-clock constraint. The complete project includes a ring-oscillator TRNG, and controlled deterministic fault patterns are inserted into selected windows of the TRNG stream for fault-response verification. Deterministic RTL simulations show complete alarm mappings of 0111111 for fixed-value patterns, 0011000 for an isolated alternating window, and 1011000 for the fourth consecutive alternating window. A parameterized capture simulation also verifies pre-event, injection, and recovery sequencing. FPGA implementation results show that the entropy-supervisor core uses 1009 LUTs and 276 flip-flops without BRAM or DSP resources, while the complete project uses 1313 LUTs, 614 flip-flops, and one BRAM tile. The design meets the 50 MHz clock constraint with a WNS of 1.079 ns and no setup or hold violations. The total on-chip power reported by Vivado is 0.076 W; without simulation-derived switching activity, this value is approximate and is not a board measurement. The results establish the functional behavior of the monitoring and decision paths. The two-bit pattern-concentration and first-order conditional-transition indicators are empirical tools for online anomaly diagnosis; neither is a min-entropy estimator, and they do not replace source-specific entropy assessment under NIST SP 800-90B.