Electrohydrodynamic (EHD) printing is an advanced micro/nanoscale additive manufacturing technique. Owing to its high-resolution capability, broad material compatibility, diverse printing modes, and low cost, it has attracted widespread attention. Nevertheless, significant challenges remain in transitioning EHD printing from the laboratory to large-scale industrial production. This paper elucidates the mechanisms of EHD printing and details control methods for high-resolution, controllable micro/nanopattern fabrication, including process-parameter optimization, rheological design of functional inks, and innovations in system architecture. We summarize recent applications in electronic devices, biomedicine, and optical components, and discuss development directions and prospects for industrial adoption.

As the density of electronic packaging continues to rise, traditional soldering techniques encounter significant challenges, leading to copper–copper direct bonding as a new high-density connection method. The high melting point of copper presents difficulties for direct diffusion bonding under standard conditions, thus making low-temperature copper–copper bonding a focal point of research. In this study, we examine the sintering process at various temperatures by constructing models with multiple nanoparticles and sintering them under different conditions. Our findings indicate that 600 K is a crucial temperature for direct copper–copper sintering. Below this threshold, sintering predominantly depends on structural adjustments driven by residual stresses and particle contact. Conversely, at temperatures of 600 K and above, the activation of rapid surface atomic motion enables further structural adjustments between nanoparticles, leading to a marked decrease in porosity. Mechanical testing of the sintered samples corroborated the structural changes at different temperatures, demonstrating that the surface dynamic motion of atoms inherent in low-temperature sintering mechanisms significantly affects the mechanical properties of nanomaterials. These findings have important implications for developing high-performance materials that align with the evolving requirements of modern electronic devices.

Integrated circuits have become indispensable in modern society owing to their formidable computational power and high integration, finding extensive applications in critical fields such as artificial intelligence and new energy vehicles. However, continued increases in integration density and reductions in physical size lead to a significantly higher heat flux density, thereby posing major challenges for thermal management and overall chip reliability. To address these thermal challenges, this study introduces an optimized manifold microchannel design. A three-dimensional conjugate heat transfer model was developed, and computational fluid dynamics simulations were performed to analyze the thermal–hydraulic performance. To mitigate temperature non-uniformity, several strategies were implemented: adjusting channel widths, employing uneven inlet gaps, and incorporating micro-fins. Results demonstrate that the optimized configuration achieves a maximum temperature reduction of 7.7 K, with peak thermal stress decreasing from 55.29 MPa to 47 MPa, effectively improving temperature uniformity. This study confirms that the proposed optimized design significantly enhances overall thermal performance, thereby offering a reliable and effective strategy for advanced chip thermal management.

Random number generators play a critical role in ensuring information security, supporting encrypted communications, and preventing data leakage. However, the random number generators widely used in hardware are faced with potential threats such as environmental disturbances and fault injection attacks. Especially in automotive-grade environments, chips encounter threat scenarios involving multidimensional fault injection, which may lead to functional failures or malicious exploitation, endangering the security of the entire system. This paper focuses on a Counter Mode Deterministic Random Bit Generator (CTR-DRBG) based on the AES-128 algorithm and implements a hardware prototype system compliant with the NIST SP 800-22 standard on an FPGA platform. Centering on typical fault modes such as temperature disturbances, voltage glitches, electromagnetic interference, and bit flips, single-dimensional and multidimensional fault injection and simulated fault injection experiments were designed and conducted. The impact characteristics and sensitivities of electromagnetic faults, voltage faults, and temperature faults regarding the output sequences of random numbers were systematically evaluated. The experimental results show that this type of random number generator exhibits modular-level differential vulnerability under physical disturbances, especially in the data transmission processes of encryption paths and critical registers, which demonstrate higher sensitivity to flip-type faults. This research provides a feasible analysis framework and practical basis for the security assessment and fault-tolerant design of random number generators, possessing certain engineering applicability and theoretical reference value.

The foundation of modern vehicle control relies on Electronic Control Units (ECUs) communicating via the Controller Area Network (CAN). However, CAN was not designed with security in mind. Limited bandwidth and lack of security make CAN vulnerable, while centralized solutions like AUTOSAR SecOC suffer from high latency. To solve this problem, we propose a novel security protocol named Self-Updating Hash Chain Layered Security Protocol (SUHC-LSP), which uses a “space-time coupled” frame structure to fit a robust authentication code into the limited CAN data field. Unlike conventional schemes that require explicit freshness negotiation during routine operation, SUHC-LSP adopts a self-updating hash-chain mechanism in which chain evolution proceeds autonomously under normal conditions. In addition, SUHC-LSP introduces a self-updating hash chain mechanism that enables freshness iteration during steady-state operation. Traditional AUTOSAR SecOC configuration schemes require additional synchronization messages and freshness counter management, whereas the approach proposed in this paper eliminates the resulting bandwidth overhead while adhering to the 8-byte CAN payload limit and ensuring message authenticity and integrity. In addition, a risk-adaptive two-layer architecture is designed to balance fast speed for local messages and strong encryption for cross-domain messages. BAN-logic and ProVerif verification show that the protocol preserves authentication, freshness, secrecy, and event-correspondence properties under the stated assumptions. Experiments on an STM32 platform show that, in a 4-device prototype, the computational overheads are 1.61 ms for intra-domain communication and 0.83 ms for inter-domain communication. Moreover, analytical overhead comparison indicates that the proposed protocol has lower sensitivity to network scale than the compared schemes.

The output quality of random-number sources directly affects the security of cryptographic systems. Physical-noise degradation, environmental disturbance, device aging, and fault injection may increase output bias, correlation, and predictability. This paper presents a resource-conscious on-chip entropy-quality supervisor for random-number source output streams. The design uses non-overlapping 1024-bit measurement windows and a shared feature engine for bit counts, directional transition counts, and run information. These features support repetition-count, adaptive-proportion, and low-toggle checks, together with two-bit pattern-concentration and first-order conditional-transition indicators, exponentially weighted moving-average trend monitoring, comprehensive scoring, and a seven-bit alarm bitmap. The RTL accepts a 32-bit valid-data interface, makes one decision every 32 valid words, and is integrated into an Artix-7 XC7A35T project configured with a 50 MHz system-clock constraint. The complete project includes a ring-oscillator TRNG, and controlled deterministic fault patterns are inserted into selected windows of the TRNG stream for fault-response verification. Deterministic RTL simulations show complete alarm mappings of 0111111 for fixed-value patterns, 0011000 for an isolated alternating window, and 1011000 for the fourth consecutive alternating window. A parameterized capture simulation also verifies pre-event, injection, and recovery sequencing. FPGA implementation results show that the entropy-supervisor core uses 1009 LUTs and 276 flip-flops without BRAM or DSP resources, while the complete project uses 1313 LUTs, 614 flip-flops, and one BRAM tile. The design meets the 50 MHz clock constraint with a WNS of 1.079 ns and no setup or hold violations. The total on-chip power reported by Vivado is 0.076 W; without simulation-derived switching activity, this value is approximate and is not a board measurement. The results establish the functional behavior of the monitoring and decision paths. The two-bit pattern-concentration and first-order conditional-transition indicators are empirical tools for online anomaly diagnosis; neither is a min-entropy estimator, and they do not replace source-specific entropy assessment under NIST SP 800-90B.