In this letter, a novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized for the first time, which can effectively suppress the subthreshold slope (SS) degradation without leakage current increase through self-adaptively current replenishing with bandgap engineering, greatly alleviating the critical issue of high average SS in conventional TFETs. Based on CMOS-compatible technology, the fabricated HS-TFETs of vertically stacked Si-Si _1-x Ge _x source can experimentally achieve superior performance with nearly constant SS over five decades of drain current, high Ion (~14μA/μm @ VDS = -1 V), and large I _on /I _off ratio (~10 ⁷ ). The proposed device with high process compatibility shows great potentials for future ultra-low power applications.

Neuromorphic computing systems have shown powerful capability in tasks, such as recognition, learning, classification and decision-making, which are both challenging and inefficient in using the traditional computation architecture. The key elements including synapses and neurons, and their feasible hardware implementation are essential for practical neuromorphic computing. However, most existing synaptic devices used to emulate functions of a single synapse and the synapse-based networks are more energy intensive and less sustainable than their biological counterparts. The dendritic functions such as integration of spatiotemporal signals and spike-frequency coding characteristics have not been well implemented in a single synaptic device and thus play an imperative role in future practical hardware-based spiking neural networks. Moreover, most emerging synaptic transistors are fabricated by nanofabrication processes without CMOS compatibility for further wafer-scale integration. Herein, we demonstrate a novel ionic-gated silicon nanowire synaptic field-effect transistor (IGNWFET) with low power consumption (<400 fJ per switching event) based on the standard CMOS process platform. For the first time, the dendritic integration and dual-synaptic dendritic computations (such as “Add” and “Subtraction”) could be realized by processing frequency coded spikes using a single device. Meanwhile, multi-functional characteristics of artificial synapses including the short-term and long-term synaptic plasticity, paired pulse facilitation and high-pass filtering were also successfully demonstrated based on 40 nm wide IGNWFETs. The migration of ions in polymer electrolyte and trapping in high-k dielectric were also experimentally studied in-depth to understand the short-term plasticity and long-term plasticity. Combined with statistical uniformity across a 4-inch wafer, the comprehensive performance of IGNWFET demonstrates its potential application in future biologically emulated neuromorphic systems.

The total ionizing dose (TID) response of bulk Si PMOS FinFETs with two fin widths and two types of fin orientation (standard and 45° rotated) is experimentally investigated under four irradiation bias conditions. The bias dependence of bulk Si PMOS FinFETs is demonstrated. The ON-bias configuration is found to be the worst irradiation bias condition. Besides, fin width dependence is illustrated. Narrow fin devices show larger threshold voltage ( $V_{{\text {th}}}$ ) shift after irradiation compared with wide fin devices. Furthermore, the fin orientation dependence of the TID response of bulk Si PMOS FinFETs is investigated. The 45° rotated transistors ( $\langle 100\rangle $ Fin) illustrate smaller irradiation-induced $V_{{\text {th}}}$ shift and transconductance ( $g_{m}$ ) decrease compared with standard transistors ( $\langle 110\rangle $ Fin). This orientation dependence is attributed to the oxidation rate and carrier mobility dependence of fin orientation. The results may deepen the understanding of the TID effect of bulk Si PMOS FinFET and offer an idea for future radiation-hardened FinFET integrated circuit (IC) fabrication.

In this letter, we investigate the robustness of silicon-on-insulator-based gate-all-around silicon nanowire transistors (GAA SNWTs) subject to electrostatic discharge (ESD) stress by thermal analysis and transmission line pulse measurements.. The thermal conductance modeling shows that heat dissipation, from channel to substrate through gate oxide, gate electrode, and buried oxide, dominates the thermal failure mechanism and thus the intrinsic ESD performance in GAA SNWTs. Accordingly, a new GAA SNWT is proposed and fabricated. A record failure current density of 18.8 mA/ $\mu \text{m}$ is achieved at a nanowire diameter of 5 nm and a gate length of 500 nm. The impact of device parameters on ESD performance is also studied to give the guidance for the future ESD design with silicon nanowire transistors.