In this article, we introduce a new analytical model for determining the threshold voltage ( ${V} {_{\text {TH}}}$ ) in charge-trap-based hybrid gate-stack enhancement-mode (E-mode) AlGaN/GaN MIS-high electron mobility transistors (HEMTs). The ${V} {_{\text {TH}}}$ expression is derived by simultaneously solving the potential balance and interfacial Gauss equations based on band and charge distribution analyses, with the stored charge in the charge-trapping layer (CTL) evaluated considering both Wentzel–Kramers–Brillouin (WKB)-based tunneling and thermally activated emission probabilities. The model examines how ${V} {_{\text {TH}}}$ depends on structural parameters across three CTL thickness regimes: thin, where CTL thickness has minimal effect, but the blocking layer thickness dominates; intermediate, where both CTL thickness and trapped charge influence ${V} {_{\text {TH}}}$ ; and thick, where trapped charge is negligible and ${V} {_{\text {TH}}}$ decreases linearly with increasing CTL thickness. The model’s accuracy was validated by TCAD simulation, and the dependence of ${V} {_{\text {TH}}}$ on various initialization voltages and temperature was analyzed. The results offer valuable guidance for optimizing the structure and designing charge-trap-based hybrid gate-stack E-mode GaN MIS-HEMTs.

To enhance the RF power properties of CMOS-compatible gold-free GaN devices, this work introduces a kind of GaN-on-Si HEMT with a low parasitic regrown ohmic contact technology. Attributed to the highly doped n⁺ InGaN regrown layer and smooth morphology of gold-free ohmic stacks, the lowest ohmic contact resistance (R_c) was presented as 0.072 Ω·mm. More importantly, low RF loss and low total dislocation density (TDD) of the Si-based GaN epitaxy were achieved by a designed two-step-graded (TSG) transition structure for the use of scaling-down devices in high-frequency applications. Finally, the fabricated GaN HEMTs on the Si substrate presented a maximum drain current (I_drain) of 1206 mA/mm, a peak transconductance (G_m) of 391 mS/mm, and a breakdown voltage (V_BR) of 169 V. The outstanding material and DC performances strongly encourage a maximum output power density (P_out) of 10.2 W/mm at 8 GHz and drain voltage (V_drain) of 50 V in active pulse mode, which, to our best knowledge, updates the highest power level for gold-free GaN devices on Si substrates. The power results reflect the reliable potential of low parasitic regrown ohmic contact technology for future large-scale CMOS-integrated circuits in RF applications.