A continuous-time multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture operating at 2-6 Gb/s has been proposed. The performance of the XTC equalizer has been measured with various spacings of FR4 channels and data rates. The crosstalk energy reutilization technique efficiently handles crosstalk and achieves high signal integrity in severe crosstalk environments where crosstalk had completely closed the data eye. Measurement results show improvement in jitter_{p- p} and vertical opening of the eye diagram by 67% UI and 58.2%, respectively, which is the best known improvement to date. The MIMO-XTC portion occupies 0.03 mm² and consumes 2.8 mW/Gbps/lane, which is two times lower than previously proposed XTC schemes.

This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL) power. A single coarse counter logic structure along with time-interleaved even/odd paths significantly reduces the complexity and speed of the TDC logic. The proposed TDC consumes only 0.44 to 24 mW for 0.077 to 24.42 ns of detection range. The multi-path GRO accelerates the oscillation speed and achieves approximately 6.2 ps of time resolution. The GRO-TDC shows -1.43 to 1.35 least-significant bits (LSB) of differential non-linearity (DNL) and -1.32 to 1.96 LSB of integral non-linearity (INL) over a 11-bit dynamic range (DR). The entire ADPLL including the proposed TDC has been fabricated in a 65 nm CMOS process and occupies 0.67 mm2 of active area. The prototype ADPLL consumes 12.22 mW from 1.2 V supply and the TDC consumes only 0.65 mW for a 50-phase offset code. A modified integrating structure in the subsequent digital loop filter (DLF) has been developed to mitigate dithering noise on Vctrl code and the measured reference spur is -69.38 dBc at 3.6 GHz center frequency. The tuning range of the implemented ADPLL is 3.5 to 4.7 GHz by using 2-bit band switching and 5-bit coarse control, while maintaining low-KDCO values to suppress in-band quantization noise. The measured root-mean-square (RMS) jitter is 0.94 ps and 0.99 ps at 3.6 GHz integer-mode and 3.60743 GHz fractional-mode respectively.

This brief analyzes a linear characteristic of the high-resolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in the time domain. A type-I digital phase locked loop (DPLL) using the CBFD is free from the issues related to the input static phase offset and the loop is unconditionally stable. Based on the loop dynamics of a DPLL with a CBFD (CB-DPLL), a jitter optimization in presence of phase noise of in-band and oscillator $1/{f}^{2}$ has been conducted. This analysis provides us with insights to design the CB-DPLL with the minimum output jitter.

A 6 Gbps frequency-locked loop (FLL) for reference-less clock recovery loop has been designed. Based on the analyzed noise characteristic of the pseudo reference clock and the effect on the FLL output, we propose design strategies to decide the speed of the pseudo clock and the loop bandwidth for low phase noise. A non-linear digital sub loop enables the FLL to converge to the optimal noise bandwidth with a fast lock time. The proto-type reference-less clock recovery loop has been fabricated in 65 nm CMOS process and the FLL occupies 0.131 mm ² chip area. The FLL consumes 12.5 mW from 1 V supply and the measured output jitter is 4.13 ps,rms at 6 GHz.

An efficient dual‐mode input and output transceiver scheme is proposed. The transceiver can achieve the data speed from 0.5 up to 4.4 Gbit/s with 0.6 V supply voltage and can support the near‐ground mode for low‐power memory interface application. The transceiver can transmit both PAM4/NRZ signals flexibly depending on the channel loss conditions. The prototype bi‐directional two‐channel transceiver is implemented in 45 nm CMOS process and occupies 0.0516 mm ² chip area. The IP shows power consumption of 2.24/2.78 mW during 4.4 Gbit/s PAM4/NRZ mode operation, each, respectively.