Single UIS and repetitive UIS experiments are performed in this article to expound physical failure mechanisms in P-GaN HEMT devices. V_peak and I_peak are used as metrics to evaluate the degradation of electrical parameters. In the single UIS tests, different load inductors, off-gate voltages, and ambient temperatures are chosen as variables to observe the failure phenomena in the device under test (DUT), while in the repeated UIS tests, the threshold voltage, on-state resistance, blocking characteristics, and gate leakage current degradation and recovery are analyzed, and it is concluded that Vth presents a negative shift, R_on and BV are restored to their initial value, and gate leakage shows a significant reduction at first and then, after a duration of lagging, gradually recovers to some extent, but is unable to achieve its initial value. Combining failure point analysis via decapping with TCAD simulation and validation, it is found that hole trapping and detrapping in the p-GaN region dominate Vth and Igss degradation, while electron traps in the buffer dominate R_on and BV degradation.

This paper investigates the short-circuit characteristics of 1.2 kV symmetrical and asymmetrical trench-gate SiC MOSFETs. Based on the self-designed short-circuit test platform, single and repetitive short-circuit tests were carried out to characterize the short-circuit capability of the devices under different electrical stresses through the short-circuit withstanding time (SCWT). Notably, the asymmetric trench structure exhibited a superior short-circuit capability under identical test conditions, achieving a longer SCWT compared to its symmetrical counterpart. Moreover, TCAD was used to model the two devices and fit the short-circuit current waveforms to study the difference in short-circuit characteristics under different conditions. For the degradation of the devices after repetitive short-circuit stresses, repetitive short-circuit pulse experiments were conducted for the two groove structures separately. The asymmetric trench devices show a positive Vth drift, increasing on-resistance, increasing C_gs and C_ds, and decreasing C_gd, while the symmetric trench devices show a negative Vth drift, decreasing on-resistance, and inverse variation in capacitance parameters. Both blocking voltages are degraded, but the gate-source leakage current remains low, indicating that the gate oxide has not yet been damaged.

Single UIS and repetitive UIS experiment are performed in this article to expound physical failure mechanisms in P-GaN Hemt devices. Vpeak versus Ipeak as the metric to evaluate the degradation of electrical parameters. In single UIS test, different load inductors, off-gate voltage and ambient temperature are chosen as variables to observe the failure phenomena in device under test(DUT), while in repeated UIS tests, threshold voltage, on-state resistant, blocking characteristics and gate leakage current degradation and recovery are concluded and analyzed that Vth presents a negatively shifting, Ron and BV will restore to their initial value, gate leakage shows a significant reduction at first and then after a duration of lagging will gradually recover to some extent but unable to achieve to its initial value. Combing failure point analysis by decaping with TCAD simulation validation, hole trapping and detrapped dominate Vth and Igss degradation, while Ron and BV degradation are dominated by electron traps in buffer.