In this article, the reliability of planar, symmetrical, and asymmetrical trench SiC mosfet s is analysed under repetitive short circuit impulses at 300 and 450 K. Both static and dynamic parameters are measured to characterize the degradation pattern of the three mosfet structures. The degradation mechanisms are analyzed and the internal electro-thermal behavior of mosfet s is revealed through TCAD models. It has been found out that there is minor degradation for planar SiC devices under both test conditions. The symmetrical trench SiC mosfet has the lowest reliability, which fails after 200 and 80 cycles at room and elevated temperature. The asymmetrical trench SiC mosfet has slightly higher reliability, failing after 1500 cycles and 500 cycles at room and elevated temperature, respectively. A comprehensive range of measurements until failure and the corresponding Silvaco TCAD analysis confirms that for both trench SiC mosfet s, the deterioration of the gate oxide is responsible for the degradations and device failure. The higher the temperature, the higher electro-thermo-mechanical stress the devices suffer.

Single UIS and repetitive UIS experiments are performed in this article to expound physical failure mechanisms in P-GaN HEMT devices. V_peak and I_peak are used as metrics to evaluate the degradation of electrical parameters. In the single UIS tests, different load inductors, off-gate voltages, and ambient temperatures are chosen as variables to observe the failure phenomena in the device under test (DUT), while in the repeated UIS tests, the threshold voltage, on-state resistance, blocking characteristics, and gate leakage current degradation and recovery are analyzed, and it is concluded that Vth presents a negative shift, R_on and BV are restored to their initial value, and gate leakage shows a significant reduction at first and then, after a duration of lagging, gradually recovers to some extent, but is unable to achieve its initial value. Combining failure point analysis via decapping with TCAD simulation and validation, it is found that hole trapping and detrapping in the p-GaN region dominate Vth and Igss degradation, while electron traps in the buffer dominate R_on and BV degradation.

In this paper, a 4H-SiC double-trench metal-oxide-semiconductor field-effect transistor (UMOSFET) with high-k gate dielectric is studied. For its low gate leakage current, strong electric field and many advantages in the application of extreme conditions, high-k gate dielectric has attracted many attentions in our MOSFETs application. Therefore, the electrical characteristics of 4H-SiC double-trench MOSFET with different gate dielectric material were compared through TCAD simulation. The simulation results had shown that with the usage of high-k gate dielectric materials, V th decreased, BV decreased, R on,sp decreased, Q gd decreased and FOM increased. Therefore, high-k gate dielectric material could be a good choice in the 4H-SiC double-trench MOSFETs manufacture for switching and power applications.

This paper investigates the short-circuit characteristics of 1.2 kV symmetrical and asymmetrical trench-gate SiC MOSFETs. Based on the self-designed short-circuit test platform, single and repetitive short-circuit tests were carried out to characterize the short-circuit capability of the devices under different electrical stresses through the short-circuit withstanding time (SCWT). Notably, the asymmetric trench structure exhibited a superior short-circuit capability under identical test conditions, achieving a longer SCWT compared to its symmetrical counterpart. Moreover, TCAD was used to model the two devices and fit the short-circuit current waveforms to study the difference in short-circuit characteristics under different conditions. For the degradation of the devices after repetitive short-circuit stresses, repetitive short-circuit pulse experiments were conducted for the two groove structures separately. The asymmetric trench devices show a positive Vth drift, increasing on-resistance, increasing C_gs and C_ds, and decreasing C_gd, while the symmetric trench devices show a negative Vth drift, decreasing on-resistance, and inverse variation in capacitance parameters. Both blocking voltages are degraded, but the gate-source leakage current remains low, indicating that the gate oxide has not yet been damaged.

This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters’ degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability.

Current conduction mechanisms of SiC metal-oxide-semiconductor (MOS) capacitors on n-type 4H-SiC with or without NO annealing have been investigated in this work. It has been revealed that Fowler-Nordheim (FN) tunneling is the dominating current conduction mechanism in high electrical fields, with barrier height of 2.67 and 2.54 eV respectively for samples with NO and without NO annealing. A higher barrier height for NO-annealed sample indicates the effect of N element on the SiC/SiO