This paper focuses on the game evolution process and its influencing factors of financial risk cooperation behavior between suppliers and manufacturers in global supply chain system. Using two‐population evolutionary game theory, the performance of supply chain members under financial risk environment is modeled. Further, the proposed financial risk game model is applied to simulation cases of global supply chain. Based on the theory analysis and simulation results, it is shown that the cooperation strategy is the optimal evolutionarily stable strategy (ESS) for all supply chain members, when facing the high financial risk. The financial risk‐sharing coefficient can be regarded as an adjuster that affects risk ESS of both suppliers and manufacturers under the low financial risk setting. By reducing the financial risk‐sharing ratio of one supply chain player, his intention of adopting cooperation strategy would be enhanced. Finally, it is observed that financial risk sharing approach may lead to the alignment among supply chain members. Therefore, setting up an effective financial risk‐sharing mechanism is beneficial to realize sustainable development of global supply chain.

The problem size of the stencil computation on GPU is limited by the GPU memory capacity, which is typically smaller than that of host memory. This paper proposes and evaluates a multi-level optimization method for stencil computation to achieve both larger problem size than GPU memory and high performance. It is based on the temporal blocking method, which has been proposed to improve memory access locality of stencil computation. It applies temporal blocking to 2 layers to improve locality of computation. Then it reuses former result to solve redundant problem. Furthermore, it parallels computation with communication by 2 additional buffers. Evaluation of 7-point stencil simulation on 3D domain shows that our new method achieves 16.74 times better performance than naive method and 1.35 times better performance than other methods on average.

To achieve real-time object detection tasks with high throughput and low latency, this paper proposes a multi-die hardware accelerator architecture. It implements three accelerators on the VU9P chip, each of which is bound to an independent super logic region (SLR). To reduce off-chip memory access and power consumption, this design uses three on-chip buffers to store the weights and intermediate result data on one hand; on the other hand, it minimizes data access and movement and maximizes data reuse. This design uses an 8-bit quantization strategy for both weights and feature maps to achieve twice the throughput and computational efficiency of a single digital signal processor (DSP). In addition, many operators are designed in the accelerator, and all of them are fully parameterized, so it is easy to extend the network, and the control of the accelerator can be realized by configuring the instruction group. By accelerating the YOLOv4-tiny algorithm, the accelerator architecture can achieve a frame rate of 148.14 frames per second (FPS) and a peak throughput of 2.76 tera operations per second (TOPS) at 200 MHz with an energy efficiency ratio of 93.15 GOPS/W. The code can be found at https://github.com/19801201/Verilog_CNN_Accelerator .

Currently, many applications implement convolutional neural networks on CPUs or GPUs while the performances are limited by the computational complexity of these networks. Compared with the implementation on CPUs or GPUs, deploying convolutional neural accelerators on FPGAs can achieve superior performance. On the other side, the multiplication operations of convolutional neural networks have been a constraint for FPGAs to achieve the better performance. In this paper, we proposed a shift convolutional neural network accelerator, which converts the multiplication operations into shift operations. Based on the shift operation, our accelerator can break the computational bottleneck of FPGAs. On Virtex UltraScale+ VU9P, our accelerator can save DSP resources and reduce memory consumption while achieving a performance of 1.18 TOPS(Tera Operations Per Second), which is an essential improvement over the other convolutional neural accelerators.