This paper presents the UJI Industrial Robotics Telelaboratory, which lets Ph.D. and Master's degree students perform robotics and computer vision tele-experiments. By using this system, students are able to program experiments remotely via the Web, in order to combine the use of a field-programmable gate array (FPGA) to provide real-time vision processing, a conveyor belt, and a Motoman industrial manipulator. This paper introduces the novel SNRP protocol (i.e., Simple Network Robot Protocol), which permits the integration of network robots and sensors within an e-learning platform in a simple and reliable manner. As long as the students are able to interact remotely with a real robotic scenario, this system helps students very much to learn robotics control techniques like visual servoing control, vision for industrial applications, and robotics manipulation. The various components of the system are connected via a 100BaseT Ethernet network and follow the SNRP protocol, which grants simple access to generic networked devices using enhanced HTTP-based connections. Moreover, the whole telelaboratory is connected to the Internet through a router that permits the user to control the networked devices according to security constraints. The SNRP architecture is compared with a Common Object Request Broker Architecture-based approach, which was used in a previous telelaboratory. This paper describes two principle contributions: the design of a novel SNRP network architecture for the intercommunication of robots and sensors within an e-learning telelaboratory and the integration of a programmable FPGA vision system, which allows students to learn not only robotic techniques but also the design of high-performance circuits for industrial vision applications.

Graphic processing units (GPUs) have become a basic accelerator both in high-performance nodes and low-power system-on-chip (SoC). They provide massive data parallelism and very high performance per watt. However, their reliability in harsh environments is an important issue to take into account, especially for safety-critical applications. In this article, we evaluate the influence of the parallelization strategy on the reliability of lower–upper (LU) decomposition on a GPU-accelerated SoC under proton irradiation. Specifically, we compare a memory bound and a compute bound implementation of the decomposition on a K20A GPU embedded on a Tegra K1 (TK1) SoC. We leverage the GPU and CPU clock frequencies both to highlight the radiation sensitivity of the GPU where we are running the benchmark and also to apply both algorithms to solve problems with the same size when exposed to the same radiation dose. Results show that more intensive use of the resources of the GPU increases the cross section. We also observed that most of the radiation-induced errors hang the operating system and even the rebooting process. Finally, we present a preliminary study of the error propagation of the LU decomposition algorithms.

Many current embedded systems comprise heterogeneous computing components including quite powerful GPUs, which enables their application across diverse sectors. This study demonstrates the efficient execution of a medium-sized self-supervised audio spectrogram transformer (SSAST) model on a low-power system-on-chip (SoC). Through comprehensive evaluation, including real time inference scenarios, we show that GPUs outperform multi-core CPUs in inference processes. Optimization techniques such as adjusting batch size, model compilation with TensorRT, and reducing data precision significantly enhance inference time, energy consumption, and memory usage. In particular, negligible accuracy degradation is observed, with post-training quantization to 8-bit integers showing less than 1% loss. This research underscores the feasibility of deploying transformer neural networks on low-power embedded devices, ensuring efficiency in time, energy, and memory, while maintaining the accuracy of the results.

Commercial off-the-shelf (COTS) system-on-chip (SoC) are becoming widespread in embedded systems. Many of them include a multicore central processing unit (CPU) and a high-end graphics processing unit (GPU). They combine high computational performance with low power consumption and flexible multilevel parallelism. This kind of device is also being considered for radiation environments where large amounts of data must be processed or compute-intensive applications must be executed. In this article, we compare three different strategies to perform matrix multiplication in the GPU of a Tegra TK1 SoC. Our aim is to analyze how the different use of the resources of the GPU influences not only the computational performance of the algorithm, but also its radiation sensitivity. Radiation experiments with protons were performed to compare the behavior of the three strategies. Experimental results show that most of the errors force a reboot of the platform. The number of errors is directly related with how the algorithms use the internal memories of the GPU and increases with the matrix size. It is also related with the number of transactions with the global memory, which in our experiments is not affected by the radiation. Results show that the smallest cross section is obtained with the fastest algorithm, even if it uses the cores of the GPU more intensively.