Division remains one of the most computationally demanding operations in digital arithmetic. Traditional algorithms, such as restoring, non-restoring, and SRT (Sweeney–Robertson–Tocher) division, are limited by sequential dependencies that reduce throughput in hardware implementations. To overcome these constraints, this work proposes a pipelined integer divider architecture that employs precomputed divisor multiples and comparator-based logic to eliminate the need for full binary adders in the quotient selection stages. The proposed design consists of a three-stage pipeline, where each stage compares the shifted partial remainder with stored multiples of the divisor (B, 2B, 3B) to generate two quotient bits per clock cycle. This approach achieves a 2× reduction in the number of computation stages compared with conventional radix-2 dividers and ensures continuous operation after an initial pipeline latency. The architecture was described in Verilog hardware description language (HDL) and implemented on a Xilinx Artix-7 (XC7A100T-1CSG324C) field-programmable gate array (FPGA) using the Xilinx ISE Design Suite 14.4. Post-synthesis simulation confirmed correct quotient and remainder generation with a maximum operating frequency of 208 MHz. The implementation occupied less than 0.3% the look-up table (LUT) resources, achieving over a twofold performance improvement compared with a non-pipelined baseline. These results demonstrate that the proposed divider provides an efficient trade-off between speed and hardware cost, making it suitable for digital signal processing and embedded computation systems.

Integer division remains one of the most computationally demanding arithmetic operations in digital computing systems. Conventional sequential dividers produce one quotient bit per clock cycle, requiring n cycles for an n-bit division. This paper proposes an architecture for a sequential integer divider capable of simultaneously generating three quotient bits per clock cycle. The proposed device comprises a dividend register (DR), a divisor multiples generator (DMG), a partial remainder and quotient digit generator (PRQDG), and a synchronization unit (SU). Unlike classical SRT dividers, which rely on a redundant quotient representation and quotient-digit selection tables, the proposed architecture performs an exact comparison of the partial remainder against the precomputed divisor multiples B-7B, thereby eliminating the growth of the selection table as the radix increases. The architecture is described in Verilog HDL and verified on a Xilinx Artix-7 FPGA using the Vivado design suite. The prototype for a 12-bit dividend and a 6-bit divisor occupies 158 LUTs and 50 flip-flops, attains a maximum clock frequency of 134.6 MHz, and is confirmed by a suite of ten tests; a division is completed in two clock cycles. The architecture is intended for use in high-speed digital computing units and specialized processors.