We propose a secure biometric data protection (SBDP) system, which uses artificial intelligence (AI) and encryption methods to prevent forgery and keep the biometric data private and intact. The proposed SBDP approach integrates deep learning-based feature extraction with robust encryption and authentication mechanisms in a single pipeline. We use the optimized convolutional neural network (OCNN) to obtain unique features from multimodal biometric inputs like fingerprints, facial photos, and retinal scans. This works well because it learns how to represent data efficiently. To reduce the risks of raw biometric exposure, we adopt a generative adversarial network (GAN) to generate synthetic biometric representations that maintain essential characteristics while reducing sensitivity to data leakage. The biometric features and images are encrypted using the ElGamal cryptosystem to provide security assurance, while the digital signature scheme based on the SHA-256 hash function is used to provide data integrity and authenticity. Experimental results show good performance of all components of the framework. The optimized CNN obtains a classification accuracy of more than 99.8%, while the GAN shows stable training behavior with the discriminator and generator losses converging to around 0.3 and 4.0, respectively. The cryptographic module guarantees encryption dependability and signature verification efficacy across all evaluated scenarios. The integrated system provides effective protection of biometric data from unauthorized access, tampering and identity forgery. The SBDP framework is a promising solution for defense, healthcare and digital identity management, ensuring secure transmission and storage of biometric data.

Integer division remains one of the most computationally demanding arithmetic operations in digital computing systems. Conventional sequential dividers produce one quotient bit per clock cycle, requiring n cycles for an n-bit division. This paper proposes an architecture for a sequential integer divider capable of simultaneously generating three quotient bits per clock cycle. The proposed device comprises a dividend register (DR), a divisor multiples generator (DMG), a partial remainder and quotient digit generator (PRQDG), and a synchronization unit (SU). Unlike classical SRT dividers, which rely on a redundant quotient representation and quotient-digit selection tables, the proposed architecture performs an exact comparison of the partial remainder against the precomputed divisor multiples B-7B, thereby eliminating the growth of the selection table as the radix increases. The architecture is described in Verilog HDL and verified on a Xilinx Artix-7 FPGA using the Vivado design suite. The prototype for a 12-bit dividend and a 6-bit divisor occupies 158 LUTs and 50 flip-flops, attains a maximum clock frequency of 134.6 MHz, and is confirmed by a suite of ten tests; a division is completed in two clock cycles. The architecture is intended for use in high-speed digital computing units and specialized processors.