In this paper, a microwave monolithic integrated circuit (MMIC) high-power amplifier (HPA) for Ku-band active radar applications based on gallium nitride on silicon (GaN-on-Si) is presented. The design is based on a three-stage architecture and was implemented using the D01GH technology provided by OMMIC foundry. Details on the architecture definition and design process to maximize delivered power are provided along with stability and thermal analyses. To optimize the amplifier performance, an asymmetry was included at the output combiner. Experimental results show that the HPA achieves a 39.5 dBm pulsed-mode output power, a peak linear gain of 23 dB, a drain efficiency of 27%, and good input/output matching in the 16–19 GHz frequency range. The chip area is 5 × 3.5 mm${}^2$ and for the measurements was mounted on a custom-made module. These results demonstrate that GaN-on-Si-based Solid-State Power Amplifiers (SSPAs) can be used for the implementation of Ku-band active radars.

This paper analyses the effects of single-event transients (SETs) on CMOS low noise amplifiers (LNA) designed for a 0.18 μ m technology. Two well-known topologies, the common-source and common-gate cascodes, have been analysed when heavy ions strike the most sensitive nodes of these structures. In order to simulate these strikes both a physics-based technology computer aided design (TCAD) tool and an electrical circuit domain simulator have been used. This way the physics information given by the TCAD tool is combined with the fast transient simulations performed in circuit simulators. To study their SET performance, the maximum voltage peak and the recovery time of the output signal were calculated for both LNAs. Additionally, a safe operating area can be defined, setting the boundaries for acceptable SETs. Radiation hardening by design techniques have been applied at the most vulnerable nodes of both LNAs. The proposed mitigation approaches make both LNAs hardened against radiation, considerably improving their SET performance.

In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases.

In this paper, a wide-band distributed model that can approximate the behaviour of square and octagonal inductors, both with and without tapering, is presented. This paper also presents a novel way of accurately modelling the lateral coupling in the substrate. The presented model can be applied to any foundry process, and its validity has been demonstrated using a novel technology, the D01GH GaN process developed by OMMIC, which has a high resistivity substrate. To do so, seventeen inductors have been designed and manufactured. The proposed model has been verified against EM simulations and measurements of the designed inductors. Comparisons show that the model can correctly estimate the behaviour of the inductor, improving the results of the EM simulations for most cases. The root mean square (RMS) error calculated across the samples when estimating the inductance is 0.0565. The RMS error for the quality factor results (2.2727) is also adequate, although there is more deviation when comparing the results with the measurements.

In this paper, a Wide-band CMOS low-noise amplifier (LNA) based on Current Conveyors (CC) is presented, in which the thermal noise of the input MOSFET is cancelled by exploiting a noise-cancelling technique. This new LNA offers the following notable advantages over existing topologies: wideband performance, with a stable frequency response from 0 to 6.2GHz and wideband input matched impedance with a total absence of passive elements; a low Noise Figure (NF) and high linearity. Comparisons with other topologies prove the effectiveness of the new implementation.