The development of wake-up receivers (WuR) has recently received a lot of interest from both academia and industry researchers, primarily because of their major impact on the improvement of the performance of wireless sensor networks (WSNs). In this paper, we present the development of three different radiofrequency envelope detection (RFED) based WuRs operating at the 868 MHz industrial, scientific and medical (ISM) band. These circuits can find application in densely populated WSNs, which are fundamental components of Internet-of-Things (IoT) or Internet-of-Everything (IoE) applications. The aim of this work is to provide circuits with high integrability and a low cost-per-node, so as to facilitate the implementation of sensor nodes in low-cost IoT applications. In order to demonstrate the feasibility of implementing a WuR with commercially available off-chip components, the design of an RFED WuR in a PCB mount is presented. The circuit is validated in a real scenario by testing the WuR in a system with a pattern recognizer (AS3933), an MCU (MSP430G2553 from TI), a transceiver (CC1101 from TI) and a T/R switch (ADG918). The WuR has no active components and features a sensitivity of about −50 dBm, with a total size of 22.5 × 51.8 mm². To facilitate the integration of the WuR in compact systems and low-cost applications, two designs in a commercial UMC 65 nm CMOS process are also explored. Firstly, an RFED WuR with integrated transformer providing a passive voltage gain of 18 dB is demonstrated. The circuit achieves a sensitivity as low as −62 dBm and a power consumption of only 528 nW, with a total area of 634 × 391 μm². Secondly, so as to reduce the area of the circuit, a design of a tuned-RF WuR with integrated current-reuse active inductor is presented. In this case, the WuR features a sensitivity of −55 dBm with a power consumption of 43.5 μW and a total area of 272 × 464 μm², obtaining a significant area reduction at the expense of higher power consumption. The alternatives presented show a very low die footprint with a performance in line with most of the state-of-the-art contributions, making the topologies attractive in scenarios where high integrability and low cost-per-node are necessary.

Nowadays, mega-constellations of Low Earth Orbit (LEO) satellites have become increasingly important to provide high-performance Internet access with global coverage. This paper provides an updated comparison of four of the largest LEO mega-constellations: Telesat, SpaceX, OneWeb and Amazon. It describes the gateway design workflow from the patch antenna to phased array analysis. Patch antennas are developed for both transmission and reception after a thorough examination of the four systems. The results of electromagnetic simulation using Advanced Design Software (ADS) Momentum are shown, including their radiation pattern. Finally, a model of the gateway phased array using SystemVue is obtained using hexagonal, circular, and square arrays. According to the required effective isotropic radiated power (EIRP) and gain, the antenna sizes for the four constellations are estimated. As an example, for SpaceX constellation, a reception antenna with 8910 radiating elements using a hexagonal distribution with a gain of 46.9 dB and a sensitivity of −113.1 dBm was obtained.

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 $\mathsf{\mu }$ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the ${\mathrm{g}}_m$/${\mathrm{I}}_D$ methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the ${\mathrm{g}}_m$/${\mathrm{I}}_D$ approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the ${\mathrm{g}}_m$/${\mathrm{I}}_D$ methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm² excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

A comparison between a fully integrated Doherty power amplifier (DPA) and outphasing power amplifier (OPA) for fifth Generation (5G) wireless communications is presented in this paper. Both amplifiers are integrated using pHEMT transistors from the OMMIC’s 100 nm GaN-on-Si technology (D01GH). After a theoretical analysis, the design and layout of both circuits are presented. The DPA uses an asymmetric configuration where the main amplifier is biased in class AB and the auxiliary amplifier is biased in class C, while the OPA uses two amplifiers biased in class B. In the comparative analysis, it has been observed that the OPA presents a better performance in terms of maximum power added efficiency (PAE), while the DPA provides higher linearity and efficiency at 7.5 dB output back-off (OBO). At a 1 dB compression point, the OPA exhibits an output power of 33 dBm with a maximum PAE of 58.3% compared to 44.2% for the DPA for an output power of 35 dBm, and at 7.5 dB OBO, the DPA achieves a PAE of 38.5%, while the OPA achieves 26.1%. The area has been optimized using absorbing adjacent component techniques, resulting in an area of 3.26 mm² for the DPA and 3.18 mm² for the OPA.

In this paper, a microwave monolithic integrated circuit (MMIC) high-power amplifier (HPA) for Ku-band active radar applications based on gallium nitride on silicon (GaN-on-Si) is presented. The design is based on a three-stage architecture and was implemented using the D01GH technology provided by OMMIC foundry. Details on the architecture definition and design process to maximize delivered power are provided along with stability and thermal analyses. To optimize the amplifier performance, an asymmetry was included at the output combiner. Experimental results show that the HPA achieves a 39.5 dBm pulsed-mode output power, a peak linear gain of 23 dB, a drain efficiency of 27%, and good input/output matching in the 16–19 GHz frequency range. The chip area is 5 × 3.5 mm${}^2$ and for the measurements was mounted on a custom-made module. These results demonstrate that GaN-on-Si-based Solid-State Power Amplifiers (SSPAs) can be used for the implementation of Ku-band active radars.