Threshold voltage ( ${V}_{\text {TH}}$ ) hysteresis affects the reliability of silicon carbide (SiC) MOSFETs. To evaluate the ${V}_{\text {TH}}$ hysteresis effect on switching characteristics, this article first investigates the ${V}_{\text {TH}}$ hysteresis in the static characteristics of three SiC MOSFETs with different gate structures. The results illustrate the density of the interface states in different gate structures. Then, the effect of ${V}_{\text {TH}}$ hysteresis on dynamic characteristics under varying OFF-state starting voltages ( ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ ) is evaluated by experiment. Furthermore, the effect mechanism of ${V}_{\text {TH}}$ hysteresis and ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ on switching characteristics is analyzed. Under the effect of the ${V}_{\text {TH}}$ hysteresis, a smaller ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ reduces ${V}_{\text {TH}}$ when the device turns on. This phenomenon leads to a reduction in the turn-on delay and consequently lowers the turn-on loss. Therefore, the ${V}_{\text {TH}}$ hysteresis is a significant factor for gate driver design of SiC MOSFETs.

Due to the remarkable performance of silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) on high temperature, it is promising in future applications in various applications. The accurate online junction temperature based on dynamic temperature-sensitive electrical parameters (TSEPs) is significant for the protection and condition monitoring, which can prolong or monitor the lifetime of SiC MOSFET devices. In this article, four different dynamic TSEPs, including turn-on delay time, turn-off delay time, and maximum current turn-on and turn-off switching rates, are theoretically analyzed taking the parasitic parameters into consideration. The experimental analysis of the influence of parasitic parameters ’ dynamic TSEPs is carried on using a buck converter test setup. Based on the theoretical and experimental analyses, a junction temperature correction method is proposed for SiC MOSFET. The online junction temperature monitoring experiments are used to verify the accuracy and effectiveness of the proposed method. The results show that the proposed correction method can largely eliminate the junction temperature monitoring error at different parasitic parameters. The maximum measurement error is reduced from 147 °C to 4.7 °C after correction.

Silicon carbide (SiC) power devices possess many beneficial properties for power electronics applications, but commercial 62-mm SiC power module packages with the direct drop-in replacement of silicon (Si) devices limit many benefits of these SiC power devices. To fully utilize the advantages of the SiC power devices, this paper presents a low-profile and high power-density packaging solution of a 62-mm 1200V/300A SiC power module with enhanced electrical and thermal performance. The design optimizations on layout, chip placement, and terminal structure are compatible with conventional module fabrication processes. An increase of power density by threefold is achieved with a low-profile package by reducing the height of the terminal connectors. Moreover, lower voltage overshoots of gate-source and drain-source of the proposed module are demonstrated due to low inductance in both gate and power loops. Thermal simulations show that the proposed module has a lower peak junction temperature and a more balanced temperature distribution among parallel devices. Finally, the commercial and fabricated modules were characterized experimentally under the same conditions. Both simulation and experimental results show the gate and power loop inductances of the proposed module are reduced by 96% and 76%, respectively. Moreover, the total switching loss and drain-source voltage overshoot are reduced by 44% and 54%, respectively, at 300 A using a 2 Ω external gate resistor.

Gate-oxide degradation has been one of the major reliability challenges of SiC mosfet s. Comprehensive and accurate localization of gate-oxide degradation under bias temperature instability (BTI) conditions is important to improve the device reliability. The split C–V [gate–source capacitance C _GS ( v _G ) and gate–drain capacitance C _GD ( v _G )] method is proposed in this article to locate gate-oxide degradation. Moreover, a BTI automated characterization system integrated I–V and split C–V test is presented. The effect of gate-oxide degradation on threshold voltage and split C–V under dc and ac BTI conditions is investigated and the degradation location is analyzed. Furthermore, the degradation simulation is conducted with technology computer aided design (TCAD) to reveal the mechanism. The results show that the different parts of split C–V can characterize degradation location, the type, and energy level of traps. The acceptor traps near valence band and donor traps near conduction band cause gate-oxide degradation above the channel and junction field effect transistor (JFET) region in positive bias temperature instability (PBTI) and Negative Bias Temperature Instability (NBTI), respectively. In ac BTI, the gate-oxide degradation at the channel region is independent of v _G polarity, while the opposite is true above JFET region. These findings help to improve the long-term operation reliability of gate oxide from the perspective of chip design and application.

Gate oxide degradation under dynamic gate stress has been demonstrated as a reliability issue for SiC MOSFETs recently. Investigating the influence of dynamic drain-source voltage stress ( V_DS ) and load current ( I_L ) involved in switching operation on gate oxide degradation is very significant to identify the way for effectively assessing gate oxide reliability. In this article, a buck converter with continuous switching condition and constant high temperature is built and operated to evaluate gate oxide degradation. Moreover, the results from buck converter are compared to results regarding AC bias temperature instability (BTI) under the same conditions for devices with different gate structures. The degradation degree of different gate oxide locations under the two operations is analyzed combining I-V and split C-V characteristics. It is found that there is consistent degradation of the gate oxide above JFET region, but depending on the operation mode, the degradation is different above channel region, indicating that VDS and I_L have different effects on different gate oxide locations. Therefore, AC BTI test cannot sufficiently evaluate gate oxide degradation and may overestimate or underestimate its reliability, depending on the device structure and fabrication process. It is necessary to investigate the gate oxide reliability in typical switching operation.