This paper addresses the influence of parameters spread on transient current distribution among parallel-connected silicon carbide (SiC) MOSFETs and proposes a chips classification method to suppress current imbalance. A comprehensive comparison of parameter spread between silicon (Si) and SiC MOSFETs is first presented. Then, a new classification criterion, referred to in this paper as distance coefficient of transfer curves (DCTC), is proposed to characterize device spread. In addition, the sensitivity analysis of transient current imbalance (TCI) to device spread is carried out. It is found that TCI increases almost linearly with increasing DCTC. Furthermore, a hierarchical cluster algorithm is developed to achieve an automated chips classification for multiple devices intended for paralleled application. This algorithm may as well facilitate the chip selection process for multiple-chip power module packaging. Moreover, the influence of operating temperature on classification is also discussed. It should be noted that chips classification needs to consider real application conditions and package parasitic. Finally, a test bench with a round layout is designed, to keep circuit layout asymmetry to a minimum, and used to experimentally verify the performance of the classification method. Experimental results validate the effectiveness of the proposed classification method for suppressing transient current imbalance.

Threshold voltage ( ${V}_{\text {TH}}$ ) hysteresis affects the reliability of silicon carbide (SiC) MOSFETs. To evaluate the ${V}_{\text {TH}}$ hysteresis effect on switching characteristics, this article first investigates the ${V}_{\text {TH}}$ hysteresis in the static characteristics of three SiC MOSFETs with different gate structures. The results illustrate the density of the interface states in different gate structures. Then, the effect of ${V}_{\text {TH}}$ hysteresis on dynamic characteristics under varying OFF-state starting voltages ( ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ ) is evaluated by experiment. Furthermore, the effect mechanism of ${V}_{\text {TH}}$ hysteresis and ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ on switching characteristics is analyzed. Under the effect of the ${V}_{\text {TH}}$ hysteresis, a smaller ${V}_{\text {G}}^{ \mathrm{\scriptscriptstyle OFF}}$ reduces ${V}_{\text {TH}}$ when the device turns on. This phenomenon leads to a reduction in the turn-on delay and consequently lowers the turn-on loss. Therefore, the ${V}_{\text {TH}}$ hysteresis is a significant factor for gate driver design of SiC MOSFETs.

With the penetrations of renewable energies and electrified transportations, there is an increasing demand for power converters with wide voltage gain range operation capabilities due to the nature of the renewable energy sources, energy storage elements, and loads. As one of the most popular isolated DC/DC converter types, this article reviews the existing important techniques for resonant type converters with wide voltage gain range operation capabilities. The existing techniques can be classified into two groups according to whether modifications are required or not on the conventional resonant converters: 1) design and control strategy optimizations: this group includes accurate analysis methods and hybrid control strategies, and no modifications on the circuit topology are required; 2) topology improvement: based on where the modifications are made, it has three different subgroups, that is, primary inverter, resonant tank, and secondary rectifier. The general operation principles for each group are discussed and some representative literatures are selected for detailed discussions. Characteristics for each group are summarized, including advantages and disadvantages. Moreover, an application-oriented discussions and recommendations are made. Guidelines for technique selections can be obtained from the analysis and discussions that presented in this article.

Due to the remarkable performance of silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) on high temperature, it is promising in future applications in various applications. The accurate online junction temperature based on dynamic temperature-sensitive electrical parameters (TSEPs) is significant for the protection and condition monitoring, which can prolong or monitor the lifetime of SiC MOSFET devices. In this article, four different dynamic TSEPs, including turn-on delay time, turn-off delay time, and maximum current turn-on and turn-off switching rates, are theoretically analyzed taking the parasitic parameters into consideration. The experimental analysis of the influence of parasitic parameters ’ dynamic TSEPs is carried on using a buck converter test setup. Based on the theoretical and experimental analyses, a junction temperature correction method is proposed for SiC MOSFET. The online junction temperature monitoring experiments are used to verify the accuracy and effectiveness of the proposed method. The results show that the proposed correction method can largely eliminate the junction temperature monitoring error at different parasitic parameters. The maximum measurement error is reduced from 147 °C to 4.7 °C after correction.

Device parameter mismatch generates current imbalance between parallel devices. In severe cases, the device that withstands excessive current may incur overcurrent failure, which poses challenges to the safety of the parallel system. To suppress the current imbalance, it is necessary to screen parallel devices to obtain approximate device parameters. This paper addresses the influence of parameter spread on the dynamic and static current distributions in parallel SiC metal- oxide- semiconductor field-effect transistors (MOSFETs) and proposes a device screening method to suppress current imbalance. First, the dispersity of device parameters that affect the dynamic and static current distributions are statistically analyzed. Then, the parameter transconductance coefficient (g) and fitting threshold voltage ( $V_{\mathrm{ th*}}$ ) that characterize the transfer curve are obtained through cubic fitting. A screening method based on g and $V_{\mathrm{ th*}}$ for suppressing dynamic current imbalance is proposed. Moreover, the relationship curve between the on-state resistance ( $R_{\mathrm{ ds}}$ ) and the drain current ( $I_{\mathrm{ d}}$ ) is linearly fitted to obtain the minimum on-state resistance ( $R_{\mathrm{ dsmin}}$ ) and the maximum on-state resistance ( $R_{\mathrm{ dsmax}}$ ) to characterize the on-state resistance under different current levels. A screening method based on $R_{\mathrm{ dsmin}}$ and $R_{\mathrm{ dsmax}}$ is proposed to suppress static current imbalance. Finally, a test bench with a symmetrical layout is designed to experimentally verify the performance of the device screening methods. The experimental results validate the effectiveness of the proposed device screening method for suppressing dynamic and static current imbalances. In addition, a comprehensive control method of suppressing the current imbalance based on device parameters and circuit parameters is proposed.

Gate-oxide degradation has been one of the major reliability challenges of SiC mosfet s. Comprehensive and accurate localization of gate-oxide degradation under bias temperature instability (BTI) conditions is important to improve the device reliability. The split C–V [gate–source capacitance C _GS ( v _G ) and gate–drain capacitance C _GD ( v _G )] method is proposed in this article to locate gate-oxide degradation. Moreover, a BTI automated characterization system integrated I–V and split C–V test is presented. The effect of gate-oxide degradation on threshold voltage and split C–V under dc and ac BTI conditions is investigated and the degradation location is analyzed. Furthermore, the degradation simulation is conducted with technology computer aided design (TCAD) to reveal the mechanism. The results show that the different parts of split C–V can characterize degradation location, the type, and energy level of traps. The acceptor traps near valence band and donor traps near conduction band cause gate-oxide degradation above the channel and junction field effect transistor (JFET) region in positive bias temperature instability (PBTI) and Negative Bias Temperature Instability (NBTI), respectively. In ac BTI, the gate-oxide degradation at the channel region is independent of v _G polarity, while the opposite is true above JFET region. These findings help to improve the long-term operation reliability of gate oxide from the perspective of chip design and application.