Despite extensive investigations of a wide variety of artificial synapse devices aimed at realizing a neuromorphic hardware system, the identification of a physical parameter that modulates synaptic plasticity is still required. In this context, a novel two-dimensional architecture consisting of a NbSe₂/WSe₂/Nb₂O₅ heterostructure placed on an SiO₂/p+ Si substrate was designed to overcome the limitations of the conventional silicon-based complementary metal-oxide semiconductor technology. NbSe₂, WSe₂, and Nb₂O₅ were used as the metal electrode, active channel, and conductance-modulating layer, respectively. Interestingly, it was found that the post-synaptic current was successfully modulated by the thickness of the interlayer Nb₂O₅, with a thicker interlayer inducing a higher synapse spike current and a stronger interaction in the sequential pulse mode. Introduction of the Nb₂O₅ interlayer can facilitate the realization of reliable and controllable synaptic devices for brain-inspired integrated neuromorphic systems.

In this study, the first sub‐60 mV dec ⁻¹ super‐steep subthreshold swing (SS) of graphene/InGaZnO (IGZO) cold‐source field‐effect transistor (CSFET) arrays is demonstrated. The linear density of states of the Dirac‐cone‐type graphene suppresses the Boltzmann thermal tail near the graphene/IGZO interface which in turn causes super‐exponentially decaying electron density with increasing energy, leading to an extremely low off current and SS value. In particular, by introducing an HfO ₂ high‐k dielectric with a low body factor, the surface potential is effectively modulated, further reducing SS by ≈46.4 mV dec ⁻¹ . Furthermore, highly uniform sub‐60 mV dec ⁻¹ SS with a yield of ≈89.1% is achieved in the IGZO CSFET 8 × 8 array devices, with a record SS value of 23.66 mV dec ⁻¹ compared to previously reported oxide‐semiconductor transistors. The proposed IGZO CSFET device is expected to drive significant advancements in high‐speed and ultralow‐power electronic circuits.

In this study, we demonstrate that an atomic-layer-deposited Al2O3 dielectric interlayer uniformly covering both the channel and contact regions effectively reduces the Schottky barrier height (SBH) of tellurium (Te) field-effect transistors (FETs), providing a facile strategy to mitigate Fermi-level pinning. An ultrathin 3 nm Al2O3 interlayer inserted between the metal electrode and Te channel leads to significantly better electrical performance than that of Te FETs with channel-only Al2O3 passivation. Specifically, the drain current increases by a factor of 2.5, while the hysteresis window of the threshold voltage is reduced from 14.4 to 8.1 V. Transmission line measurements reveal a substantial decrease in contact resistance from 23.9 to 1.47 MΩ•μm, which is attributed to the reduction in SBH from 57.8 to 19.9 meV. These results highlight the importance of simultaneous channel and contact interface engineering and establish the Al2O3 interlayer as an effective approach for realising reliable p-type Te FETs.